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| CXA2150AQ CRT DRIVER Description The CXA2150AQ is a bipolar IC which integrates base-band Y/C signal processing, RGB signal processing, horizontal sync signal processing that supports 15.7/31.5/33.75/37.9/45kHz, and a vertical deflection circuit that supports 50/60/100/120Hz into a single chip. This IC has been developed for DTV, and realizes the configuration of a high-end TV system that supports 960i, 1080i, 720p, etc. in addition to 480i. 64 pin QFP (Plastic) Features * I2C bus supported * YCbCr input offset adjustment circuit * LTI and CTI circuits * Sharpness f0 switching circuit that supports band width of various input sources * Color (Cr signal) dependent sharpness circuit * Coring circuit for VM signal * AKB system * Various ABL functions * Two sets of analog RGB inputs * Horizontal sync processing that supports 15.7/31.5/33.75/37.9/45kHz * Vertical deflection circuit that supports 50/60/100/120Hz * Quick responsed VAGC when switching channels etc. * Deflection compensation circuit capable of supporting various wide modes * For flat-TV suitable various VSAW waveform and parabola output Applications Color TVs (4:3, 16:9) Structure Bipolar silicon monolithic IC Absolute Maximum Ratings (Ta = 25C) * Supply voltage VCC -0.3 to +10 V * Operating temperature Topr -20 to +75 C * Storage temperature Tstg -65 to +150 C * Allowable power dissipation PD 1.7 W (when mounted on a 50mm x 50mm board) * Voltages at each pin -0.3 to VCC9, VCC_OUT + 0.3 V Operating Conditions Supply voltage VCC9, VCC_OUT 9.0 0.5 VCC5 5.0 0.25 V V Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E00819-PS VM_MOD VM_OUT Block Diagram YF_OFF CLP_C DPDT_OFF BPH R1_IN G1_IN B1_IN YSYM1 R2_IN G2_IN B2_IN 4 2 YSYM2 15 14 13 16 12 17 10 9 8 7 6 5 VM CLP * DPIC_LEV * AGING_W * AGING_B * PICTURE * SUB_CONT Y * LRGB2_LEV * VM_LEV * VM_DLY * VM_COR * VM_F0 * VM_LMT CLP 0 to -9dB Y_IN 20 CLP Y R * DC_TRAN * Y_OFFSET Y * SHARPNESS * PRE/OVER * SHP_F0 * SHP_F1 * SHP_CD * CD_OFF * GAMMA_L * DCOL * PLIMIT_LEV * BRIGHT * SUB_BRIGHT * R, G, B_CUTOFF * BLK_BTM * PIC_ON * R, G, B_ON * AKBOFF * BLK_OFF 58 IK_IN 64 R_OUT 63 G_OUT 62 B_OUT SHP LTI DPIC MAT G B * WB_SW * R, G, B_DRIVE CB_IN 21 CTI CbCr * CTI_LEV * CTI_MODE CLP COL HUE AXIS R-Y G-Y B-Y * LTI_LEV, MODE * SYSTEM YS YM PIC DRV YS YM CR_IN 22 CbCr GAM DCOL PLIMT BRT AKB BLK PABL SCL 26 SDA 25 I2C BUS DECODER 11 PABL_FIL 56 ABL_IN ABL * ABL_MODE * ABL_TH * P_ABL * S_ABL F0 23 * COLOR_AXIS * COLOR NTSC-JPN * HUE * CB_OFFSET NTSC-US * CR_OFFSET PAL NTSC-PJ CLP PULSE BLK PULSE 57 ABL_FIL 59 SABL_IN 60 PRE_RGB 38 L2_FIL 39 HP_IN 34 HPROT F1 24 * AFC_MODE Vcc9 VREG5 VBIAS Vcc5 V_OSC V_AGC GND_V GND_H VPROT VSAW0 IREF_YC IREF_HV Vcc_OUT GND_OUT GND_SIG V_DRV+ V_DRV- VSAW1 VCOMP_IN -2- 2.7MHz VCO * H_POSITION * AFC_BOW * AFC_ANGLE * HBLK_SW * AFC_COMP HS_IN 28 TIMING DECODER AFC_FIL 32 AFC CERA 33 LOOP2 * CLP_PHASE * CLP_SHIFT * CLP_GATE * LEFT_BLK * RIGHT_BLK * SYNC_PHASE SCP 27 SCP HD 40 H_DRV 36 HCOMP_IN EW_FUNC * H_SIZE * EW_DC * PIN_PHASE * PIN_AMP * UP, LO_UCP, UCG * H_COMP * UP, LO_CPIN * UP_POL * PIN_COMP VTIM 54 * V_SCROLL * V_ASPECT * UP, LO_VLIN * JMP_SW * ZOOM_SW * ASP_SW 47 EW_DRV VS_IN 42 5V - DEF 5V - SIG 9V - DEF COUNT AGC VOSC W-FUNC * VSAW0, 1_DCL, H * VSAW0, 1_AMP DF_PARA 46 DF_PARA * V_FREQ * AKBTIM * UP, LO_BLK * VBLK_SW * RST_SW * V_SIZE * V_LIN * V_POSITION * V_COMP * S_CORRECTION * V_ON * VDRV_SW MP_PARA V-FUNC VSAW0, 1 * MP_PARA_DC, AMP 45 MP_PARA IREF REG HC_PARA 55 19 48 49 61 1 3 41 44 35 53 52 37 50 51 * HC_PARA_DC, AMP, PHASE 43 HC_PARA 18 31 29 30 CXA2150AQ CXA2150AQ Pin Configuration HCOMP_IN VCOMP_IN MP_PARA HC_PARA DF_PARA EW_DRV HPROT 34 GND_H VSAW1 VSAW0 VPROT GND_V V_AGC V_OSC H_DRV L2_FIL HP_IN VS_IN 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 33 CERA V_DRV- 52 V_DRV+ 53 VTIM 54 Vcc9 55 ABL_IN 56 ABL_FIL 57 IK_IN 58 SABL_IN 59 PRE_RGB 60 Vcc_OUT 61 B_OUT 62 G_OUT 63 R_OUT 64 32 AFC_FIL 31 IREF_HV 30 VBIAS 29 VREG5 28 HS_IN 27 SCP 26 SCL 25 SDA 24 F1 23 F0 22 CR_IN 21 CB_IN 20 Y_IN 1 GND_OUT 2 YSYM2 3 GND_SIG 4 B2_IN 5 G2_IN 6 R2_IN 7 YSYM1 8 B1_IN 9 G1_IN 10 R1_IN 11 PABL_FIL 12 DPDT_OFF 13 YF_OFF 14 VM_OUT 15 VM_MOD 16 CLP_C 17 BPH 18 IREF_YC 19 Vcc5 -3- CXA2150AQ Pin Description Pin No. 1 Symbol GND_OUT Equivalent circuit Description GND for RGB_OUT output stage YS2/YM2 control input. When the input level reaches the YM level, VM is OFF. VCC_OUT VCC5 25 25 2 YSYM2 2 2k 12.5k 7.5k VIH 2.3V RGB2_IN selected YS2: OFF VIL 1.5V Internal RGB signal selected 3 GND_SIG VCC_OUT 100k VCC5 500 4 5 6 B2_IN G2_IN R2_IN 4 5 6 2k Analog R2, G2 and B2 signal inputs. Input a 0.7Vp-p, 100 IRE (no sync) signal via a capacitor. The pedestal is clamped to 3.2V. Input voltage range: less than 5V 20k YS1/YM1 control input. When the input level reaches the YM level, VM is OFF. VCC_OUT VCC5 25 25 7 YSYM1 7 VIH 2.3V RGB1_IN selected YS1: OFF VIL 1.5V Internal RGB signal selected 2k 12.5k 7.5k -4- CXA2150AQ Pin No. Symbol Equivalent circuit VCC_OUT 100k VCC5 500 Description 8 9 10 B1_IN G1_IN R1_IN 8 9 10 2k Analog R1, G1 and B1 signal inputs. Input a 0.7Vp-p, 100 IRE (no sync) signal via a capacitor. The pedestal is clamped to 3.75V. Input voltage range: less than 5V 80k 3V VCC_OUT VCC5 270 11 PABL_FIL 2k 11 25k 33k Peak hold for peak ABL. A capacitor and resistor are connected between this pin and GND to form a LPF. VCC_OUT 12.5 VCC5 12.5 12 DPDT_OFF 12 Muting of the dynamic picture operation (black expansion) and DC transmission ratio signal interval detection can be controlled by this pin. MUTE: ON VIH 1V MUTE: OFF VIL 0.4V Input voltage range: 0 to 5V 2k 25 0.7V VCC_OUT VCC5 For turning off the VM, sharpness and color. Ternary inputs are supported. : OFF : ON VM, SHP : OFF : ON COLOR VIH 3V VIL 2V VIH 1.0V VIL 0.4V 13 YF_OFF 13 2k 2.5V 0.7V Input voltage range: 0 to 5V VCC_OUT VCC5 500 500 14 VM_OUT 14 500 30k VM output. The differential waveforms of the Y signal are output with a positive polarity. The amplitude and phase of this waveform can be adjusted by the I2C bus. Allowable load current: -1 to +1mA -5- CXA2150AQ Pin No. Symbol Equivalent circuit VCC_OUT VCC5 Description 45k 15 VM_MOD 15 50k 2V 2.5V VM level modulation. Outputs are 0 at 1.5V or less, modulated from 1.5 to 3.5V, nonmodulated at 3.5V or more. At 1.5V or more output level can be adjusted by VM_LEV (I2C bus control) Input voltage range: 0 to 5V VCC_OUT 500 VCC5 25k 1k 16 CLP_C 16 Connect a capacitor for Y system clamp. This capacitor also sets the DC transmission ratio. 40k 2k VCC_OUT 1k 17 BPH 2k 17 50k Connect a capacitor to GND for black detection of the dynamic picture (black stretch) 2V VCC_OUT 18 IREF_YC 150 18 50k 20k Reference current setting for Y/color difference signal processing system. Connect to GND via the 4.7k resistor (such as a metal film resistor) with an error of less than 1%. 19 Vcc5 Power supply for Y/color difference, RGB systems and I2C bus block. -6- CXA2150AQ Pin No. Symbol Equivalent circuit VCC_OUT 100k VCC5 500 Description 20 21 22 Y_IN CB_IN CR_IN 20 21 22 2k 80k External Y, Cb and Cr inputs Input 0.7Vp-p, 100 IRE Y, Cb and Cr signals (when Cb and Cr are at 100% color bar) via a capacitor. The pedestal is clamped to 3.5V. Input voltage range: less than 5V VCC9 VREG5 75k 23 24 F0 F1 2k 23 24 120k 75k 3.75V Horizontal free-running frequency setting (See Table 1 on page 44.) VCC5 I2C bus protocol SDA (Serial Data) input 25 SDA 4k 25 2.5V VIH 3V VIL 1.5V VOL 0.6V VCC5 26 SCL 26 I2C bus protocol SCL (Serial Clock) input 4k 2.5V VIH 3V VIL 1.5V VCC9 27 SCP 150 27 1.2k 1k 34k Sand castle pulse output The approximately 0 to 5V CLP pulse is output superimposed on the approximately 0 to 2.5V HBLK and VBLK pulses. Allowable load current: -0.5 to +2mA -7- CXA2150AQ Pin No. Symbol VCC9 Equivalent circuit Description HSYNC input Input at the sync phase. 25k 28 HS_IN 28 200k 5.6p Positive polarity input VIH 2.6V VIL 0.6V Input DC coupled VCC9 500 150 30 35k 29 30 VREG5 VBIAS 29 Connect a NPN-Tr for the external feedback between Pin 30 (VBIAS) and Pin 29 (VREG5) to form 5V shunt regulator. Connect a capacitor of 100F between Pin 29 (VREG5) and GND. 1.25V To Vcc for H system and the reference voltage for V system VCC9 31 IREF_HV 31 150 4.9k 2k 11k 2k 1.35V Reference current setting for H, V deflection systems. A 10k resistor with an error of less than 1% (such as a metal film resistor) is connected between this pin and GND. VCC9 1.2k 32 AFC_FIL 1.2k 32 100k 3V 50 AFC lag-lead filter Connect the RC for the lag-lead filter. -8- CXA2150AQ Pin No. Symbol Equivalent circuit VCC9 4k 60k Description 33 CERA 33 400 Connect a 2.7MHz ceramic oscillator. VCC9 34 HPROT 69.5k 34 32.5k HD output hold-down signal input When this pin is 2V or more for a 7V cycle or longer, the hold-down function operates so that the HD output is held to High Z. In addition, the R, G and B outputs are completely blanked and "1" is output to the status register HNG. To cancel this status, turn the IC power off and then on again. VCC9 35 VPROT 35 2k 2k V protect input. When the protect function operates, the R, G and B outputs are completely blanked and "1" is output to the status register VNG. See Fig. 14 on page 59 for the input conditions. VCC9 2k 36 HCOMP_IN 36 38k 10k 42.5k Voltage input for high voltage fluctuation compensation High voltage compensation is performed for the EW_DRV signal DC amplitude and H_DRV signal phase. The control characteristics can be varied by H_COMP, PIN_COMP and AFC_COMP, respectively. Input voltage range: 0 to 5V VCC9 2k 37 37 VCOMP_IN 38k 9.7k 13.4k Voltage input for high voltage fluctuation compensation High voltage compensation is performed for the V_DRV signal amplitude. The control characteristics can be varied by V_COMP. Input voltage range: 0 to 5V -9- CXA2150AQ Pin No. Symbol Equivalent circuit VCC9 Description Filter for AFC 2nd loop Connect to GND via a capacitor. The AFC phase can also be controlled from this pin by leading current in and out of this capacitor. As the pin voltage rises, the picture shifts to the right. As the pin voltage falls, the picture shifts to the left. 500 38 L2_FIL 1.2k 38 25 3.3V VCC9 VREG5 30k 39 HP_IN 39 30k 1.3V H deflection pulse input for H AFC Input low level = 0V and high level = 5V pulse directly or a 5Vp-p pulse via an approximately 0.1F capacitor. VCC9 150 40 H_DRV 40 50k 20k H drive signal output This pin is output by an open collector. Set high level to 5V 41 GND_H VCC9 VREG5 GND for H deflection system. VSYNC input Input at the sync phase. Positive polarity input VIH 2.6V VIL 0.6V Input DC coupled 42 VS_IN 42 2k 1.65V 50k VCC9 43 45 46 HC_PARA MP_PARA DF_PARA 43 45 46 150 35k 200 General-purpose V parabola wave output Allowable load current: -0.2 to +2.6mA - 10 - CXA2150AQ Pin No. 44 Symbol GND_V Equivalent circuit Description GND for V deflection system VCC9 47 EW_DRV 150 47 51k V parabola wave output This is used to compensate the horizontal amplitude and the horizontal pin distortion. Allowable load current: -0.2 to +2.6mA 300 25 VCC9 8k 48 V_OSC 270 48 1.2k 10 V sawtooth wave generation. Connect to GND via a 0.1F capacitor. For the capacitor, use a PP (polypropylene) capacitor, or similar capacitor with a small tan. VCC9 2k 49 V_AGC 2k 49 Sample-and-hold for AGC which maintains the V sawtooth wave at a constant amplitude Connect to GND via a 0.1F capacitor. 110k VCC9 50 VSAW0 50 150 17k 40k 200 V sawtooth wave (VSAW0) output Allowable load current: -0.2 to +2.6mA VCC9 51 VSAW1 51 150 17k 40k 200 V sawtooth wave (VSAW1) output Allowable load current: -0.2 to +2.6mA - 11 - CXA2150AQ Pin No. Symbol VCC9 Equivalent circuit Description 52 V_DRV- 52 150 17k 55.1k 300 V sawtooth wave output (opposite polarity of V_DRV+) Allowable load current: -0.3 to +1.7mA VCC9 53 V_DRV+ 53 150 17k 55.1k 300 V sawtooth wave output (opposite polarity of V_DRV-) Allowable load current: -0.3 to +1.7mA VCC9 54 VTIM 150 54 V timing pulse output Positive polarity pulses from 0 to 5V. This pin corresponds to VBLK position of RGB output during high period. 18k 2k 6k 100k 55 Vcc9 VCC_OUT VCC5 Power supply for V deflection system. 70k 56 ABL_IN 2k 56 2k 50 ABL control signal input This pin functions as the average value. The ABL_IN threshold voltage can be varied by the I2C bus ABL_TH. Input voltage range: 0 to 5V VCC_OUT VCC5 200k 57 ABL_FIL 10k 57 2k 45k Connect a capacitor to form the LPF for the ABL_IN input signal. - 12 - CXA2150AQ Pin No. Symbol Equivalent circuit VCC_OUT 3.4V Description 58 IK_IN 58 2k 40k The reference pulses are returned to this pin. The CRT cathode current IK is converted to a voltage and input via a capacitor. This signal is clamped to 2.8V at the V retrace timing of the V blanking. Input voltage range: less than 5V VCC_OUT 3.1V 59 SABL_IN 59 200k 2k 9k SABL compensation signal input PRE_RGB output signal (Pin 60) can be input via a external filter. Input voltage range: 0 to 5V VCC_OUT 2k 1.2k 60 PRE_RGB 60 1.2k 100k 2k 30k Mixed RGB signal output for high voltage fluctuation compensation and SABL compensation. Allowable load current: -0.8 to +0.4mA 61 VCC_OUT VCC_OUT Power supply for RGB system output stage. 1k 62 63 64 B_OUT G_OUT R_OUT 62 63 64 500 5k R, G and B signal outputs. A 2.6Vp-p signal is output at 100 IRE. Allowable load current: -3.7 to +5mA 3.7m - 13 - Electrical Characteristics Measurement conditions: Ta = 25C, VCC9 = VCC_OUT = 9V, VCC5 = 5V, GND_OUT = GND_SIG = GND_H = GND_V = 0V Measures the following after setting the I2C bus register as shown in "I2C bus Register Initial Settings". Symbol Measurement conditions Min. 55 18 17 4.8 5 27 33 52 38 5.2 80 115 mA mA mA V 19 Measure the pin inflow current. Measurement contents Max. Typ. ICC5 ICC9 ICCreg VREG 29 Measure the pin voltage. 55, 61 Measure the pin inflow current. Measure the collector current 29 of the external NPN-Tr. Measurement pin No. Item Unit 1 5V system current consumption 2 9V system current consumption 3 5V regulator current consumption 4 5V regulator voltage Deflection system items fHFR1 fHFR2 fHFR3 fHFR4 40 fHFR5 AFC_MODE = 0, F0: Open, F1: Open Input HSYNC Normalize the pull-in range when the HSYNC input frequency is shifted from the free-running frequency. (Confirm the HLOCK = 1.) 5 AFC_MODE = 0, F0: Open, F1: 0V AFC_MODE = 0, F0: 0V, F1: Open AFC_MODE = 0, F0: Open, F1: 5V Measure the output frequency. Horizontal free-running frequency 1 AFC_MODE = 0, F0: 0V, F1: 0V 15.4 31.1 33.4 37.2 44.7 15.74 31.5 33.83 37.6 45.1 16.1 31.9 34.2 38.0 45.5 kHz kHz kHz kHz kHz 6 Horizontal free-running frequency 2 7 Horizontal free-running frequency 3 - 14 - fHR Hdduty tCLPW Measure the pulse width for the section where the SCP CLP output is high level, and normalize it with the horizontal cycle. tCLPW 8 Horizontal free-running frequency 4 9 Horizontal free-running frequency 5 10 Horizontal sync pull-in range -- 3 -- % 11 H_DRV output pulse duty Measure the pulse duty of H_DRV output. 43.4 43.74 44 % 12 SCP CLP output pulse width 3.2 3.7 4.2 % 13 VSCPM VSCPL SCP CLP output high level VSCPH Measure the SCP CLP output high level. Measure the SCP BLK output high level. Measure the SCP output low level. 27 4.7 2.35 VSCPM VSCPH VSCPL 5 2.5 0.05 0.2 -- 2.65 0.4 V V V 14 SCP BLK output high level CXA2150AQ 15 SCP output low level No. Symbol Measurement contents Measure the V_DRV output Vp-p Item Min. Max. Typ. Unit Measurement conditions Measurement pin 16 VDp-p V_DRV output amplitude VDp-p 1.07 1.2 1.3 52, 53 VSYNC V 17 V_DRV+ 8.6ms VDdc V_DRV output center potential VDdc 3.39 3.5 3.63 V Measure the EW_DRV output Vp-p 18 Input VSYNC. 47 VSYNC EW_DRV output amplitude VEWp-p 0.39 VEWp-p 0.54 0.65 V - 15 - VEWdc 8.6ms 19 EW_DRV output center potential 3.78 VEWdc 4 4.16 V 20 VTIM output high level VTIMH 4.65 54 5 5.05 V 21 VTIM output low level VTIML VTIMH VTIML 0.15 0.25 0.35 V CXA2150AQ No. Measurement contents Min. Typ. Max. Item Symbol Measurement conditions Measurement pin Unit Signal system items 22 100 IRE signal input to Y_IN (Pin 20) 100 50 RGB output 2.56 62, 63, 64 95 Staircase wave input to Y_IN (Pin 20) V2 V1 VLIN = V1 x 100 V2 x 2 VRGB Measure the output level. 2.18 2.84 V 23 RGB linearity VLIN 100 104 % 24 63 GL2 50 IRE/8MHz RGB1 gain 100 IRE signal input to G2_IN (Pin 5), YSYM2 (Pin 2) = 5V Compare the output level to VRGB GL1 100 IRE signal input to G1_IN (Pin 9), YSYM1 (Pin 7) = 5V Compare the output level to VRGB -0.8 -0.8 -0.2 -0.1 0.3 0.8 dB dB 25 RGB2 gain - 16 - VVM 14 Sine wave to Y_IN (Pin 20) Y_IN (Pin 20) 26 VM output 1.75 Measure the VM_OUT level. 2.56 3.15 V VB 27 CB_IN (Pin 21) CR_IN (Pin 22) Cb = 572mVp-p Cr = 406mVp-p HUE center B 62 B = tan-1 VB level with Cr input VB level with Cb input -8 -4.7 -1 deg 28 VBRT-R VBRT-G VBRT-B VBLK-R BRIGHT center Rch 64 63 62 VREFP VBLK VPED -420 -420 -420 64 VBRT = VPED - VREFP -250 -250 -250 200 400 -45 -45 -45 550 mV mV mV mV 29 BRIGHT center Gch 30 BRIGHT center Bch CXA2150AQ 31 RGB output VBLK level Electrical Characteristics Measurement Circuit Signal sources DC SHIFT HP GEN 9V 2.7MHz 470 33 CERA 15k 0.47 VSYNC are all GND unless otherwise specified in the Measurement conditions column of Electrical Characteristics. VSAW1 VSAW0 EW_DRV DF_PARA MP_PARA HC_PARA 5V 5V 0.1 0.1 0.1 0.01 100 100 100 100 100 100 100 100 2.7k 51 VS_IN HP_IN L2_FIL 50 49 48 47 46 45 44 43 42 41 40 3.3k 39 38 37 36 35 34 V_AGC V_OSC H_DRV VSAW1 VSAW0 GND_V VPROT GND_H HPROT 100 52 100 100 54 VTIM 0.1 55 Vcc9 100 4.7 57 ABL_FIL 58 IK_IN 0V 100 59 SABL_IN 100 60 PRE_RGB 0.1 61 Vcc_OUT 100 100 62 B_OUT 100 63 G_OUT 100 B2_IN G2_IN R2_IN 64 R_OUT GND_SIG GND_OUT YSYM2 YSYM1 56 ABL_IN V_DRV- 53 V_DRV+ EW_DRV DF_PARA MP_PARA HC_PARA VCOMP_IN HCOMP_IN V_DRV- 100 AFC_FIL 32 0V 10k IREF_HV 31 0.68 VBIAS 30 VREG5 29 HS_IN 28 SCP 27 100 SCL 26 100 SDA 25 100 F1 24 100 F0 23 CR_IN 22 CB_IN 21 0.1 100 0.0047 V_DRV+ VTIM 9V 100 9V 5V HSYNC SCP SCL SDA 0V 0V 0.1 0.1 Y_IN 20 0.1 Cr Cb B1_IN G1_IN R1_IN PABL_FIL DPDT_OFF YF_OFF VM_OUT VM_MOD CLP_C BPH IREF_YC CRTDC 2V 1 0.1 100 2 3 4 5 0.1 0.1 6 100 7 0.1 8 0.1 9 10 0.1 11 12 100 13 100 14 15 100 16 0.47 17 4.7 18 19 4.7k 0.47 0.1 CXA2150AQ 3.3M VM 5V 100 0V 0V 0V 0V 5V Vcc5 - 17 - 10k 0.1 0.1 PRE_RGB 9V 9V 1.5k 5.1k Y CXA2150AQ Electrical Characteristics Measurement Input Signals 16.67ms = 562.5HS (60Hz) 3HS VS 5Vp-p 29.63s (33.75kHz) 2s HS 5Vp-p Y signal 18s 100 IRE (700mV) FLAT-FIELD 6s - 18 - CXA2150AQ DC SHIFT 9V 47 8 Vcc 7 OUT2 6 IN2X IN1 5 IN2 GND PC358 OUT1 1.5V 0.9V To VPROT 0.3V 20k 20k 20k 20k 1.9V 20k From V_DRV+ 2.9V 3.5V IN1X 1 2 3 4 4.1V HP GEN. To AFC_IN 5V 47 2200p 10k H_DRV 16 VDD 15 2T1 14 2T2 13 2CD 12 2A 11 2B 10 2Q 9 2Q AFC_IN Width 4.5s Vss 1Q 1Q Delay 3s 74HC4538BP 1CD 1T1 1T2 1A 4 1B 5 9V 2200p From H_DRV 1 2 3 6 7 8 10k - 19 - CXA2150AQ Electrical Characteristics Measurement Conditions "I2C bus Register Initial Settings" Register name PIC_ON R_ON G_ON B_ON DCOL WB_SW GAMMA_L PICTURE BLK_BTM HUE COL_AXIS COLOR CTI_LEV BRIGHT S_ABL SHARPNESS LTI_LEV R_DRIVE PLIMIT_LEV G_DRIVE ABL_MODE B_DRIVE CTI_MODE SUB_BRIGHT GAMMA R_CUTOFF LTI_MODE G_CUTOFF DPIC_LEV B_CUTOFF DC_TRAN SUB_CONT LRGB2_LEV P_ABL ABL_TH No. of bits 1 1 1 1 2 1 1 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 4 4 4 4 Setting 1 1 1 1 0 0 0 3Fh 0 1Fh 3 1Fh 0 1Fh 0 1Fh 0 29h 3 29h 0 29h 0 1Fh 0 1Fh 0 1Fh 0 1Fh 0 7h Fh Fh 0 Description R, G, B outputs on R output on G output on B output on DCOL off OFF GAMMA fine adjustment off Max. Min. Center NTSC Japan Center CTI off Center SABL off Center LTI off 0dB Max. 0dB Picture/Only 0dB B/W both sides improvement Center GAMMA off Center B/W both sides improvement Center OFF Center DC transmission ratio 100% Center 0dB Max. Min. - 20 - CXA2150AQ Register name CB_OFFSET AGING_W AGING_B CR_OFFSET SYSTEM Y_OFFSET VM_LEV SHP_F0 CD_OFF SHP_CD SHP_F1 PRE/OVER VM_COR VM_F0 VM_LMT VM_DLY AKB_TIM BLK_OFF AKBOFF UP_BLK LO_BLK V_SIZE V_ON EW_DC V_POSITION VSAW0_DCH V_LIN S_CORRECTION H_SIZE UP_UCP PIN_AMP LO_UCP UP_CPIN UP_UCG LO_CPIN LO_UCG No. of bits 6 1 1 6 2 4 2 1 1 2 2 2 2 2 2 2 5 1 1 4 4 6 1 1 6 2 4 4 6 2 6 2 6 2 6 2 Setting 1Fh 0 0 1Fh 2 7h 3 1 1 0 0 1 0 0 3 0 0h 0 0 0h 0h 1Fh 1 0 1Fh 1 7h 0h 1Fh 0 1Fh 0 1Fh 0 1Fh 0 Center OFF OFF Center HD mode Center Max. 16MHz Description SHP_CD function off OFF OFF 1:1 OFF Min. Maximum limit VM output delay Max. Bch REF-P 10H Blanking on AKB mode VBLK-end 0H after Bch REF-P VBLK-start 0H before VSYNC Center V_DRV output on OFF Center Center Center Min. Center Most inside point compensated Center Most inside point compensated Center Min. Center Min. - 21 - CXA2150AQ Register name PIN_PHASE UC_POL VBLK_SW H_POSITION CLP_SHIFT SYNC_PHASE AFC_BOW AFC_MODE AFC_ANGLE RST_SW LEFT_BLK CLP_PHASE RIGHT_BLK CLP_GATE HBLK_SW V_ASPECT ZOOM_SW JMP_SW V_SCROLL VFREQ UP_VLIN LO_VLIN V_COMP H_COMP VSAW0_DCL VSAW1_DC VSAW0_AMP PIN_COMP VSAW1_AMP AFC_COMP MP_PARA_DC MP_PARA_AMP HC_PARA_DC ASP_SW VDRV_SW HC_PARA_AMP HC_PARA_PHASE No. of bits 6 1 1 6 1 2 6 2 6 1 6 2 6 1 1 6 1 1 6 2 4 4 4 4 4 4 5 3 5 3 4 4 6 1 1 6 6 Setting 1Fh 0 1 1Fh 0 0 1Fh 2 1Fh 0 1Fh 3 1Fh 0 1 0h 0 0 1Fh 1 0h 0h 0h 0h Fh 7h Fh 0 Fh 0 7h 0h 1Fh 0 0 1Fh 1Fh Center Description H-size small on compensated parts UP/LO_BLK only Center CLP_PHASE settings HSYNC delay 0% Center Medium gain Center Retrace after VSYNC Center Min. Center Gating function off HBLK control enable Min. ZOOM_SW off JMP_SW off Center 60Hz mode Min. Min. Compensation off Compensation off Center Center Amplitude off Compensation off Amplitude off Compensation off Center Amplitude off Center OFF OFF Amplitude off Center - 22 - CXA2150AQ Definition of I2C bus Registers Slave address 86H: Slave Receiver 87H: Slave Transmitter Control Register (Register Tables : Undefined) Sub Address XXX00000 XXX00001 XXX00010 XXX00011 XXX00100 XXX00101 XXX00110 XXX00111 XXX01000 XXX01001 XXX01010 XXX01011 XXX01100 XXX01101 XXX01110 XXX01111 XXX10000 XXX10001 XXX10010 XXX10011 XXX10100 XXX10101 XXX10110 XXX10111 XXX11000 XXX11001 XXX11010 XXX11011 XXX11100 XXX11101 XXX11110 XXX11111 XX100000 XX100001 XX100010 XX100011 XX100100 XX100101 XX100110 XX100111 XX101000 XX101001 XX101010 XX101011 XX101100 XX101101 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh Bit 7 1 Bit 6 0 UP_VLIN V_COMP VSAW0_DCL VSAW0_AMP VSAW1_AMP MP_PARA_DC HC_PARA_DC HC_PARA_AMP HC_PARA_PHASE Bit 5 INTER Bit 4 HCENT Bit 3 HLOCK Bit 2 IKR V_LIN H_SIZE PIN_AMP UP_CPIN LO_CPIN PIN_PHASE H_POSITION AFC_BOW AFC_ANGLE LEFT_BLK RIGHT_BLK V_ASPECT V_SCROLL LO_VLIN H_COMP VSAW1_DC PIN_COMP AFC_COMP MP_PARA_AMP ASP_SW 0 0 Bit 1 HNG VDRV_SW 0 0 Bit 0 VNG UP_BLK V_SIZE V_POSITION SHP_CD VM_COR Y_OFFSET VM_F0 AKBTIM 0 SUB_CONT P_ABL CB_OFFSET CR_OFFSET VM_LEV SHP_F1 VM_LMT LO_BLK V_ON S_CORRECTION UP_UCP LO_UCP UP_UCG LO_UCG UC_POL VBLK_SW CLP_SHIFT SYNC_PHASE AFC_MODE 0 RST_SW CLP_PHASE CLP_GATE HBLK_SW ZOOM_SW JMP_SW VFREQ EW_DC VSAW0_DCH Bit 7 PIC_ON Bit 6 R_ON Bit 5 G_ON HUE COLOR BRIGHT SHARPNESS R_DRIVE G_DRIVE B_DRIVE SUB_BRIGHT R_CUTOFF G_CUTOFF B_CUTOFF LRGB2_LEV ABL_TH AGING_W SHP_F0 AGING_B CD_OFF SYSTEM PRE/OVER VM_DLY BLK_OFF AKBOFF Bit 4 B_ON Bit 3 DCOL Bit 2 Bit 1 WB_SW Bit 0 GAMMA_L PICTURE BLK_BTM COL_AXIS CTI_LEV S_ABL LTI_LEV PLIMIT_LEV ABL_MODE CTI_MODE GAMMA LTI_MODE DPIC_LEV DC_TRAN Status Register - 23 - CXA2150AQ Description of Registers Register name (Number of bits) 1. Y Signal Block Registers SYSTEM (2) Selects the signal band 0 = NORMAL mode 1 = FF mode 2 = HD mode 3 = DTV mode Sharpness gain control 00h = -10dB 1Fh = +2dB 3Fh = +8dB Sharpness f0 setting 0 = 3MHz@NORMAL mode 1 = 4MHz@NORMAL mode High f0 (4.2/5.6MHz@NORMAL mode) sharpness gain control 0 = 0dB 3 = +3dB Sharpness gain control in part of high color saturation When Cr input signal is 100% color. 0 = 0dB 3 = +6dB SHP_CD ON/OFF 0 = ON 1 = OFF LTI (Luminance Transient Improvement) control 0 = LTI off 1 = LTI weak 2 = LTI medium 3 = LTI strong LTI mode setting 0 = both of black and white side improved 1 = black side improved 2 = white side improved 3 = prohibited - 24 - Sharpness f0 (SHP_F0 = 0) 3MHz 6MHz 12MHz 18MHz Description SHARPNESS (6) SHP_F0 (1) SHP_F1 (2) SHP_CD (2) CD_OFF (1) LTI_LEV (2) LTI_MODE (2) CXA2150AQ VM_LEV (2) VM_OUT level control 0 = VM off 1 = Weak 2 = Medium 3 = Strong VM_OUT phase control; defined by difference in phase from R_OUT 0 = Short 3 = Long VM_OUT coring level setting 0 = OFF 1 = 5% coring 2 = 10% coring 3 = 15% coring Coring level not changed if limiter level changed. VM_OUT f0 setting 0 = Low 1 = Medium 2 = High 3 = prohibited VM_OUT limiter level setting 0 = OFF 1 = 83% 2 = 67% 3 = 50% DC_OFFSET canceling for Y signal 0h = -32mV 7h = 0mV Fh = +37mV Dynamic picture (black expansion) control 0 = OFF 1 = 25 IRE knee down 2 = 30 IRE knee down 3 = 35 IRE knee down Y system DC transmission ratio setting 0 = 103% 1 = 100% 2 = 90% 3 = 80% - 25 - VM_DLY (2) VM_COR (2) VM_F0 (2) VM_LMT (2) Y_OFFSET (4) DPIC_LEV (2) DC_TRAN (2) CXA2150AQ PRE/OVER (2) Pre-Shoot/Over-Shoot ratio setting 0 = 1:1.5 1 = 1:1 2 = 1.5:1 3 = 2:1 White (80 IRE) output aging mode ON/OFF switch 0 = OFF 1 = ON All black (0 IRE) output aging mode ON/OFF switch 0 = OFF 1 = ON AGING_W (1) AGING_B (1) 2. Color Difference Block Registers COL_AXIS (2) Color detection axis setting 0 = mode for NTSC Projector 1 = mode for PAL/SECAM 2 = mode for NTSC US 3 = mode for NTSC JAPAN HUE control 00h = -33deg. Flesh color appears red. 1Fh = Center 3Fh = +33deg. Flesh color appears green. Color gain control 00h = Color OFF 1Fh = 0dB 3Fh = +4.8dB HUE (6) COLOR (6) CTI_LEV (2) CTI (Chrominance Transient Improvement) setting 0 = CTI off 1 = CTI weak 2 = CTI medium 3 = CTI strong CTI mode setting 0 = both of black and white side improved 1 = black side improved 2 = white side improved 3 = prohibited - 26 - CTI_MODE (2) CXA2150AQ CB_OFFSET (6) DC_OFFSET canceling for Cb signal 00h = Bch output DC -62mV Gch output DC +10mV 1Fh = Bch output DC 0mV Gch output DC 0mV 3Fh = Bch output DC +64mV Gch output DC -12mV (@PICTURE = 3F, COLOR = 1F, COL_AXIS = 3) DC_OFFSET canceling for Cr signal 00h = Rch output DC -62mV Gch output DC +20mV 1Fh = Rch output DC 0mV Gch output DC 0mV 3Fh = Rch output DC +66mV Gch output DC -24mV (@PICTURE = 3F, COLOR = 1F, COL_AXIS = 3) CR_OFFSET (6) 3. RGB Block Registers PIC_ON (1) RGB output including AKB reference pulse ON/OFF (0 for power ON reset) 0 = RGB output OFF (complete blanking status) 1 = RGB output ON Rch video output ON/OFF (AKB reference pulse cannot be turned ON/OFF) 0 = Rch video output OFF 1 = Rch video output ON Gch video output ON/OFF (AKB reference pulse cannot be turned ON/OFF) 0 = Gch video output OFF 1 = Gch video output ON Bch video output ON/OFF (AKB reference pulse cannot be turned ON/OFF) 0 = Bch video output OFF 1 = Bch video output ON Dynamic color mode setting 0 = Dynamic Color OFF 1 = ON1 R: 98%, G: 100%, B: 102.5% 2 = ON2 R: 97%, G: 100%, B: 105% 3 = ON3 R: 96%, G: 100%, B: 106% Picture gain control (enabled for input signal excluding LRGB2) 00h = -13dB 3Fh = 0dB RGB output bottom limiter level control (for Blanking and Signal) 0 = (AKB reference pulse DC voltage) -1.25V 3 = (AKB reference pulse DC voltage) -0.65V - 27 - R_ON (1) G_ON (1) B_ON (1) DCOL (2) PICTURE (6) BLK_BTM (2) CXA2150AQ PLIMIT_LEV (2) RGB signal amplitude limiter level setting 0 = 115 IRE 1 = 123 IRE 2 = 130 IRE 3 = 136 IRE ABL mode setting 0 = PICTURE ABL ONLY mode 1 = PICTURE/BRIGHT mode 1 (BRIGHT ABL gain min.) : weak 2 = PICTURE/BRIGHT mode 2 (BRIGHT ABL gain middle) : medium 3 = PICTURE/BRIGHT mode 3 (BRIGHT ABL gain max.) : strong BRIGHT control 00h = -14 IRE 1Fh = 0 IRE 3Fh = +14 IRE RGB output GAMMA correction amount control 0 = OFF 1 = Min. (+5 IRE for 40 IRE input) 2 = Mid. (+10 IRE for 40 IRE input) 3 = Max. (+15 IRE for 40 IRE input) GAMMA differential correction ON/OFF 0 = OFF 1 = ON (+2.5 IRE for 40 IRE input) Rch drive gain control 00h = -4.67dB 29h = 0dB (2.56Vp-p at PICTURE max.) 3Fh = +1.33dB Gch drive gain control 00h = -4.67dB 29h = 0dB (2.56Vp-p at PICTURE max.) 3Fh = +1.33dB Bch drive gain control 00h = -4.67dB 29h = 0dB (2.56Vp-p at PICTURE max.) 3Fh = +1.33dB SUB_BRIGHT control 00h = -14 IRE 1Fh = 0 IRE 3Fh = +14 IRE - 28 - ABL_MODE (2) BRIGHT (6) GAMMA (2) GAMMA_L (1) R_DRIVE (6) G_DRIVE (6) B_DRIVE (6) SUB_BRIGHT (6) CXA2150AQ R_CUTOFF (6) Rch cut-off control (Rch reference pulse level control on IK_IN (Pin 58)) 00h = -10dB 1Fh = 0dB 3Fh = +6dB Gch cut-off control (Gch reference pulse level control on IK_IN (Pin 58)) 00h = -10dB 1Fh = 0dB 3Fh = +6dB Bch cut-off control (Bch reference pulse level control on IK_IN (Pin 58)) 00h = -10dB 1Fh = 0dB 3Fh = +6dB Sub picture control 0h = -0.9dB 7h = 0dB Fh = +1.2dB Picture level control for LRGB2 0h = -8dB Fh = 0dB RGB output level detection DC setting for PEAK-ABL 0h = 4.8V DC Fh = 6.6V DC Threshold voltage adjustment for ABL_IN input 0h = Vth 0.8V Fh = Vth 1.9V S_ABL gain setting 0 = S_ABL OFF 3 = S_ABL gain max. White balance offset setting 0 = OFF Normal color temperature 1 = ON Low color temperature R: 100%, G: 90%, B: 70% Automatic cut-off/Manual cut-off setting 0 = Automatic cut-off (AKB ON) 1 = Manual cut-off (AKB OFF) Blanking ON/OFF SW when AKBOFF = 1 0 = HV blanking ON 1 = HV blanking OFF (Blanking period: approximately 8 IRE) - 29 - G_CUTOFF (6) B_CUTOFF (6) SUB_CONT (4) LRGB2_LEV (4) P_ABL (4) ABL_TH (4) S_ABL (2) WB_SW (1) AKBOFF (1) BLK_OFF (1) CXA2150AQ 4. Deflection Block Registers AKBTIM (5) AKB Bch reference pulse timing setting (Counted from rising edge of VS_IN) 00h = 10H : 0Fh = 25H : 1Fh = 41H VBLK position control for top of picture, when VBLK_SW = 1 (Set number of lines blanked after Bch reference pulse.) (480i: every 1H / Others: every 2H) 0h = 0H : 7h = 7H/14H : Fh = 15H/30H VBLK position control for bottom of picture, when VBLK_SW = 1 (Set number of lines blanked before VSYNC.) (480i: every 1H / Others: every 2H) 0h = 0H : 7h = 7H/14H : Fh = 15H/30H Vertical amplitude adjustment (V_DRV signal gain adjustment) 00h = -15% Vertical picture size decreases 1Fh = 0% Amplitude: 1.2Vp-p, center DC = 3.5V (when V_ASPECT = 00h and ASP_SW = 0) 3Fh = +15% Vertical picture size increases Vertical position adjustment (V_DRV signal DC bias adjustment) 00h = -0.1V Picture position falls, V_DRV+ output DC down 1Fh = 0V Center DC = 3.5V 3Fh = +0.1V Picture position rises, V_DRV+ output DC up Vertical linearity adjustment (Gain adjustment for V_DRV signal secondary component) 0h = 112% (Bottom/top of picture) Top of picture compressed; bottom of picture expanded 7h = 100% (Bottom/top of picture) Fh = 88% (Bottom/top of picture) Top of picture expanded; bottom of picture compressed - 30 - UP_BLK (4) LO_BLK (4) V_SIZE (6) V_POSITION (6) V_LIN (4) CXA2150AQ S_CORRECTION (4) Vertical S correction amount adjustment (Gain adjustment for V_DRV signal S component) 0h = Tertiary component amplitude added to the V_DRV signal is 0. Fh = Tertiary component amplitude added to the V_DRV signal is Maximum. V_DRV signal oscillation stop ON/OFF switch 0 = V_DRV Oscillation stopped 1 = V_DRV Output EW_DRV signal DC level down 0 = Normal 1 = -1.2V Horizontal amplitude adjustment (EW_DRV signal DC bias adjustment) 00h = -0.5V Horizontal picture size decreases, EW_DRV signal output DC down 1Fh = 0V EW_DRV signal center DC: 4V 3Fh = +0.5V Horizontal picture size increases, EW_DRV signal output DC up Horizontal pin distortion compensation amount adjustment (EW_DRV signal gain adjustment) 00h = 190mVp-p Compensation amount min. 1Fh = 470mVp-p When V_ASPECT = 00h 3Fh = 750mVp-p Compensation amount max. High voltage fluctuation compensation amount setting for horizontal pin distortion (EW_DRV signal amplitude compensation) 0h = OFF 7h = -10% EW_DRV signal amplitude compensation amount when HCOMP_IN = 0V Horizontal pin distortion compensation amount adjustment for top edge of picture (EW_DRV signal gain adjustment for top edge of picture) 00h = -0.33V Horizontal size for top of picture decreases (Compensation amount max.) 1Fh = 0V 3Fh = +0.33V Horizontal size for top of picture increases (Compensation amount min.) Horizontal pin distortion compensation amount adjustment for bottom edge of picture (EW_DRV signal gain adjustment for bottom edge of picture) 00h = -0.25V Horizontal size for bottom of picture decreases (Compensation amount max.) 1Fh = 0V 3Fh = +0.25V Horizontal size for bottom of picture increases (Compensation amount min.) - 31 - V_ON (1) EW_DC (1) H_SIZE (6) PIN_AMP (6) PIN_COMP (3) UP_CPIN (6) LO_CPIN (6) CXA2150AQ UP_UCP (2) Horizontal pin distortion compensation position adjustment for extreme top edge of picture (EW_DRV signal compensation position for extreme top edge of picture) 0 = -20% Point of inflection (Position from video center, when vertical period: 100%) 3 = -33% Horizontal pin distortion compensation position adjustment for extreme bottom edge of picture (EW_DRV signal compensation position adjustment for extreme bottom edge of picture) 0 = +20% Point of inflection (Position from video center, when vertical period: 100%) 3 = +33% Horizontal pin distortion compensation amount adjustment for extreme top edge of picture (EW_DRV signal gain adjustment for extreme top edge of picture) 0 = 0V Compensation amount 0 3 = 0.26V Compensation amount max. (When UP_UCP = 0, UC_POL = 0/1, V_ASPECT = 2F) Horizontal pin distortion compensation amount adjustment for extreme bottom edge of picture (EW_DRV signal gain adjustment for extreme bottom edge of picture) 0 = 0V Compensation amount 0 3 = 0.26V Compensation amount max. (When LO_UCP = 0, UC_POL = 0/1, V_ASPECT = 2F) Horizontal pin distortion compensation polarity setting for extreme top and bottom edge of picture 0 = Horizontal size for top and bottom edge of picture decreases 1 = Horizontal size for top and bottom edge of picture increases Horizontal trapezoidal distortion compensation adjustment (EW_DRV signal center timing adjustment) 00h = 1.1ms advance Horizontal size for top of picture increases Horizontal size for bottom of picture decreases 1Fh = Compensation OFF EW_DRV center adjusted time when V_ASPECT = 00h and VFREQ is 60Hz 3Fh = 1.1ms delay Horizontal size for top of picture decreases Horizontal size for bottom of picture increases Horizontal position adjustment (AFC phase control) (See Fig. 13 on page 58, 100%: H period) 00h = -0.5% Picture position compensated to right (Video delayed with respect to HD.) 1Fh = +2.5% 3Fh = +5.5% Picture position compensated to left (Video advanced with respect to HD.) HSYNC delay amount setting with respect to video (100%: H period) 0 = 0% 1 = -3.125% LO_UCP (2) UP_UCG (2) LO_UCG (2) UC_POL (1) PIN_PHASE (6) H_POSITION (6) SYNC_PHASE (1) - 32 - CXA2150AQ AFC_BOW (6) Vertical line slope compensation amount adjustment (HAFC phase control by parabola wave, 100%: H period) 00h = Top and bottom of picture advanced 1.5% with respect to picture center 1Fh = No compensation 3Fh = Top and bottom of picture delayed 1.5% with respect to picture center Vertical line slope compensation amount adjustment (HAFC phase control by sawtooth wave, 100%: H period) 00h = Top of picture advanced 1.5%, bottom of picture delayed 1.5% with respect to picture center 1Fh = No compensation 3Fh = Top of picture delayed 1.5%, bottom of picture advanced 1.5% with respect to picture center AFC loop gain control 0 = H free-running mode 1 = Small gain 2 = Medium gain 3 = Large gain High voltage fluctuation compensation amount setting for horizontal position (HCOMP_IN = 0V, 100%: H period) 0h = 0% No compensation 7h = +0.75% Picture position compensated to left HBLK width control for left side of picture when HBLK_SW = 1 (See Fig. 13 on page 58, 100%: H period) 00h = +17.8% HBLK width max. 1Fh = +12.8% Center 3Fh = +7.8% HBLK width min. HBLK width control for right side of picture when HBLK_SW = 1 (See Fig. 13 on page 58, 100%: H period) 00h = -2.7% HBLK width min. 1Fh = -7.7% Center 3Fh = -12.7% HBLK width max. HBLK width control ON/OFF switch during 4:3 software full display mode on a 16:9 CRT 0 = HBLK generated from HP_IN 1 = HBLK is made by processing the pulse generated from HP_IN and the pulse set by LEFT_BLK and RIGHT_BLK with OR logic. Internal clamp pulse phase control (See Fig. 13 on page 58, 100%: H period) 0 = +5% 3 = +2% - 33 - AFC_ANGLE (6) AFC_MODE (2) AFC_COMP (3) LEFT_BLK (6) RIGHT_BLK (6) HBLK_SW (1) CLP_PHASE (2) CXA2150AQ CLP_SHIFT (1) Internal clamp pulse start phase setting (100%: H period) 0 = CLP_PHASE settings 1 = CLP_PHASE settings - 3.125% Switch for gating internal clamp pulse with input HSYNC 0 = No gated with input HSYNC 1 = Gated with input HSYNC Vertical frequency setting 0 = 50Hz 1 = 60Hz 2 = 100Hz 3 = 120Hz Aspect ratio control 00h = 75% 16:9 CRT Full 2Fh = 100% 4:3 CRT Full 3Fh = 106% Switch to correspond to the signal with low effective video ratio 0 = OFF 1 = ON V_DRV signal amplitude is 10% up when V_ASPECT = 0, and BLK for top and bottom for picture are 22 lines added. Zoom mode ON/OFF switch for 16:9 CRT (V_DRV signal top and bottom squeeze mode ON/OFF) 0 = Zoom OFF 1 = Zoom ON Reference pulse jump mode ON/OFF switch 0 = Jump mode OFF 1 = Jump mode ON On a 16:9 CRT, jump mode compresses the V_DRV signal amplitude to 67% On a 4:3 CRT, jump mode compresses the V_DRV signal amplitude to 75% Vertical picture scroll control 00h = -0.16V Scroll toward bottom of picture 1Fh = 0V 3Fh = +0.16V Scroll toward top of picture Vertical linearity control for top of picture 0h = 100% (Bottom/top of picture) Fh = 125% (Bottom/top of picture) Top of picture compressed Vertical linearity control for bottom of picture 0h = 100% (Bottom/top of picture) Fh = 73% (Bottom/top of picture) Bottom of picture compressed - 34 - CLP_GATE (1) VFREQ (2) V_ASPECT (6) ASP_SW (1) ZOOM_SW (1) JMP_SW (1) V_SCROLL (6) UP_VLIN (4) LO_VLIN (4) CXA2150AQ V_COMP (4) High voltage fluctuation compensation amount setting for vertical picture size 0h = 0% Fh = -12% V_DRV signal amplitude compensation amount when VCOMP_IN = 0V High voltage fluctuation compensation amount setting for horizontal picture size (EW_DRV signal DC bias compensation) 0h = 0V Fh = -0.3V EW_DRV signal DC compensation amount when HCOMP_IN = 0V VSAW0 waveform DC component control high 2 bit VSAW0 waveform DC component control low 4 bit 0h and VSAW0_DCH = 0 = -1.1V VSAW0 signal output DC down Fh and VSAW0_DCH = 1 = 0V VSAW0 signal center DC4V Fh and VSAW0_DCH = 3 = +1.1V VSAW0 signal output DC up VSAW1 waveform DC component 0h = -1.1V VSAW1 signal output DC down 7h = 0V VSAW1 signal center DC4V Fh = +1.1V VSAW1 signal output DC up VSAW0 waveform SAW component amplitude 00h = 0.9Vp-p Right falling SAW component amplitude 0Fh = 0Vp-p No VSAW0 signal SAW component 1Fh = 0.9Vp-p Right rising SAW component amplitude VSAW1 waveform SAW component amplitude 00h = 0.9Vp-p Right falling SAW component amplitude 0Fh = 0Vp-p No VSAW1 signal SAW component 1Fh = 0.9Vp-p Right rising SAW component amplitude V parabola for middle pin DC bias control 0h = -1V MP_PARA signal output DC down 7h = 0V MP_PARA signal center DC 2.5V Fh = +1V MP_PARA signal output DC up V parabola for middle pin gain control 0h = 0Vp-p No parabola wave component Fh = 0.55Vp-p Downward convex parabola wave amplitude V parabola for raster center DC bias control 00h = -1V HC_PARA signal output DC down 1Fh = 0V HC_PARA signal center DC 3.5V 3Fh = +1V HC_PARA signal output DC up - 35 - H_COMP (4) VSAW0_DCH VSAW0_DCL (2) (4) VSAW1_DC (4) VSAW0_AMP (5) VSAW1_AMP (5) MP_PARA_DC (4) MP_PARA_AMP (4) HC_PARA_DC (6) CXA2150AQ HC_PARA_PHASE (6) V parabola for raster center SAW component amplitude control 00h = 0.7Vp-p Right rising SAW component amplitude 1Fh = 0Vp-p No HC_PARA signal SAW component 3Fh = 0.7Vp-p Right falling SAW component amplitude HC_PARA_AMP (6) V parabola for raster center amplitude control 00h = 0.35Vp-p Downward convex parabola wave amplitude 1Fh = 0Vp-p No parabola wave component 3Fh = 0.35Vp-p Upward convex parabola wave amplitude V_DRV+, - signal jump voltage ON/OFF switch 0 = VDRV jump OFF 1 = VDRV jump ON Amplitude from the retrace timing to Bch reference pulse just behind increases 5% VBLK width control ON/OFF switch 0 = VBLK is set as internal VDRV limited timing when ZOOM_SW = 1 1 = VBLK is set by UP_BLK and LO_BLK VDRV retrace start setting switch 0 = 0.75H Retrace start after input VSYNC 1 = 6.25H Retrace start before input VSYNC VDRV_SW (1) VBLK_SW (1) RST_SW (1) 5. Status Registers INTER (1) Input signal interlace/progressive identification 0 = Input signal: Progressive 1 = Input signal: Interlace High-low comparison between the input HSYNC frequency and the HVCO frequency (Valid when HVCO is locked.) 0 = HVCO free-running frequency is lower than input HSYNC frequency. 1 = HVCO free-running frequency is higher than input HSYNC frequency. Lock status between HSYNC and HVCO 0 = IC free-running status 1 = Locked to HSYNC AKB operation status 0 = Unstable AKB loop 1 = Stable AKB loop Signal input status to HPROT pin 0 = Normal status 1 = Abnormal signal input to HPROT pin Signal input status to VPROT pin (See Fig. 14 on page 59.) 0 = Normal status 1 = Abnormal signal input to VPROT pin - 36 - HCENT (1) HLOCK (1) IKR (1) HNG (1) VNG (1) CXA2150AQ Description of Operation 1. Power-on Sequence The CXA2150AQ does not have an internal power-on sequence. Therefore, the entire power-on sequence is controlled by the set microcomputer (I2C bus controller). 1) Power-on reset The IC is reset during power-on and the RGB output are all blanked. Horizontal deflection output H_DRV starts to oscillate, but is free-running so that oscillation is not synchronized even if an unstable signal is input to HS_IN during power-on. In vertical deflection system, VTIM starts to output, but V_DRV is DC output. Bus registers which are set by the power-on reset are as follows. PIC_ON R_ON G_ON B_ON GAMMA_L CD_OFF BLK_OFF AKBOFF V_ON EW_DC VBLK_SW SYNC_PHASE CLP_SHIFT AFC_MODE RST_SW VFREQ VSAW0_DCH VSAW0_DCL VSAW1_DC VSAW0_AMP VSAW1_AMP = = = = = = = = = = = = = = = = = = = = = 0: 0: 0: 0: 0: 0: 0: 0: 0: 1: 0: 0: 0: 0: 0: 1: 1: Fh: 7h: Fh: Fh: RGB all blanking ON Rch video blanking ON Gch video blanking ON Bch video blanking ON GAMMA fine adjustment OFF SHP_CD function ON In AKB OFF-mode, blanking function is ON. AKB function ON (Auto-cut-off mode) V_DRV oscillation stopped mode EW_DRV signal DC level down In ZOOM, the blanking slicing internal VSAW is used. The delay amount compensation between video and HSYNC is 0. CLP_PHASE settings H_DRV oscillation free-running mode V_DRV signal starts to retrace after VSYNC 60Hz mode VSAW0 DC level center VSAW1 DC level center No VSAW0 signal SAW component No VSAW1 signal SAW component - 37 - CXA2150AQ 2) Bus register data transfer The register setting sequence differs according to the TV-set sequence. Register settings for the following sequence are shown as an example. Set sequence Power-on Degauss V_DRV oscillation CXA2150AQ register settings Reset status in 1) above. Reset status in 1) above. The CRT is degaussed in the completely darkened condition. The IC is set to the power-on initial settings. A sawtooth wave is output to V_DRV and the IC waits for the vertical deflection to stabilize. "R, G, B_ON" are set to 0, "PIC_ON" is set to 1 and reference pulse is output from R, G, B_OUT. Then, the IC waits for the cathode to warm up and the beam current to start flowing. Status register "IKR" is monitored. IKR = 0: Unstable IKR = 1: Stable Note that the time until "IKR" returns to 1 differs according to the initial status of the cathode. R, G, B_ON are set to 1 and the video signal is output from R, G, B_OUT. AKB operation start AKB loop stable Video output 3) Power-on initial settings The initial settings listed here for power-on when V_DRV starts to oscillate are reference value; the actual settings may be determined as needed according to the conditions under which the set is to be used. PIC_ON R_ON G_ON B_ON DCOL WB_SW GAMMA_L PICTURE BLK_BTM HUE COL_AXIS COLOR = = = = = = = = = = = = 0 0 0 0 0 0 0 0 0 1Fh 3 1Fh RGB all blanked Rch video output blanked Gch video output blanked Bch video output blanked Dynamic Color OFF OFF GAMMA fine adjustment OFF Max. (User control) Min. Center (User control) NTSC Japan Center (User control) - 38 - CXA2150AQ CTI_LEV BRIGHT S_ABL SHARPNESS LTI_LEV R_DRIVE PLIMIT_LEV G_DRIVE ABL_MODE B_DRIVE CTI_MODE SUB_BRIGHT GAMMA R_CUTOFF LTI_MODE G_CUTOFF DPIC_LEV B_CUTOFF DC_TRAN SUB_CONT LRGB2_LEV P_ABL ABL_TH CB_OFFSET AGING_W AGING_B CR_OFFSET SYSTEM Y_OFFSET VM_LEV SHP_F0 CD_OFF SHP_CD SHP_F1 PRE/OVER VM_COR VM_F0 VM_LMT VM_DLY AKB_TIM BLK_OFF AKBOFF UP_BLK LO_BLK V_SIZE V_ON EW_DC = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 0 1Fh 0 1Fh 0 29h 3 29h 1 29h 0 1Fh 0 1Fh 0 1Fh 0 1Fh 0 7h Fh Fh 0 1Fh 0 0 1Fh 2 7h 3 0 0 0 0 0 0 0 3 0 0h 0 0 0h 0h 1Fh 1 0 CTI OFF Center (User control) SABL OFF Center (User control) LTI OFF 0dB (Adjust) Max. 0dB (Adjust) Picture/Bright ABL mode (Bright ABL Gain min.) 0dB (Adjust) B/W both sides improvement Center (Adjust) GAMMA OFF Center (Adjust) B/W both sides improvement Center (Adjust) Black expansion OFF Center (Adjust) DC transmission ratio 100% Center (Adjust) 0dB Max. Min. Center (Adjust) OFF OFF Center (Adjust) HD mode Center (Adjust) Max. 12MHz SHP_CD function ON OFF OFF 1:1 OFF Min. Max, limit VM_OUT delay Max. Bch REF-P 10H Blanking ON AKB mode VBLK-end 0H after Bch REF-P VBLK-start 0H before VSYNC Center (Adjust) V_DRV output ON OFF - 39 - CXA2150AQ V_POSITION = VSAW0_DCH = V_LIN = S_CORRECTION = H_SIZE = UP_UCP = PIN_AMP = LO_UCP = UP_CPIN = UP_UCG = LO_CPIN = LO_UCG = PIN_PHASE = UC_POL = VBLK_SW = H_POSITION = SYNC_PHASE = CLP_SHIFT = AFC_BOW = AFC_MODE = AFC_ANGLE = RST_SW = LEFT_BLK = CLP_PHASE = RIGHT_BLK = CLP_GATE = HBLK_SW = V_ASPECT = ZOOM_SW = JMP_SW = V_SCROLL = VFREQ = UP_VLIN = LO_VLIN = V_COMP = H_COMP = VSAW0_DCL = VSAW1_DC = VSAW0_AMP = PIN_COMP = VSAW1_AMP = AFC_COMP = MP_PARA_DC = MP_PARA_AMP = HC_PARA_DC = ASP_SW = VDRV_SW = HC_PARA_AMP = HC_PARA_PHASE = 1Fh 1 7h 7h 1Fh 0 1Fh 0 1Fh 0 1Fh 0 1Fh 0 1 1Fh 0 0 1Fh 2 1Fh 0 1Fh 3 1Fh 0 1 0h 0 0 1Fh 1 0h 0h 0h 0h Fh 7h Fh 0 Fh 0 7h 0h 1Fh 0 0 0 0 Center (Adjust) Center Center (Adjust) Center (Adjust) Center (Adjust) Most inside compensation point Center (Adjust) Most inside compensation point Center (Adjust) Min. Center (Adjust) Min. Center (Adjust) H-size small on compensation parts UP/LO_BLK only Center (Adjust) HSYNC delay 0% CLP_PHASE settings Center (Adjust) Medium gain Center (Adjust) Retrace after VSYNC Center (Adjust) Min. Center (Adjust) Gate function OFF HBLK control enable 16:9 CRT (Min.) ZOOM_SW OFF JUMP_SW OFF Center (User Control) 60Hz mode Compensation OFF Compensation OFF Compensation OFF Compensation OFF Center Center Amplitude OFF Compensation OFF Amplitude OFF Compensation OFF Center Amplitude OFF Center OFF OFF Amplitude OFF Center - 40 - CXA2150AQ 2. Various Mode Settings The CXA2150AQ contains I2C bus registers for deflection compensation which can be set for various wide modes. Wide mode setting registers can be used separately from registers for normal picture distortion adjustment, and once picture distortion adjustment has been performed in full mode, wide mode settings can be made simply by changing the corresponding register data. * Vertical picture distortion adjustment registers (V_DRV) V_SIZE, V_POSITION, S_CORRECTION, V_LIN * Horizontal picture distortion adjustment registers (EW_DRV) H_SIZE, EW_DC, PIN_AMP, UP_CPIN, LO_CPIN, PIN_PHASE * Wide mode setting registers V_ASPECT, ZOOM_SW, HBLK_SW, V_SCROLL, JUMP_SW, VBLK_SW, UP_VLIN, LO_VLIN, LEFT/RIGHT_BLK, UP/LO_BLK Examples of various modes are listed below. These modes are described using 480 Iines as essential number of display scanning lines. Wide mode setting register data is also listed, but adjustment values may differ slightly due to IC variation. The standard setting data differs for 16:9 CRTs and 4:3 CRTs. Register V_ASPECT V_SCROLL ZOOM_SW UP_VLIN LO_VLIN JUM_SW VBLK_SW HBLK_SW LEFT_BLK RIGHT_BLK 16:9 CRT 0h 1Fh 1 0h 0h 0 1 1 1Fh 1Fh 4:3 CRT 2Fh 1Fh 0 0h 0h 0 1 1 1Fh 1Fh 1) 16:9 CRT full mode This mode reproduces the full 480 Iines on a 16:9 CRT. 4:3 images are reproduced by vertical compression. Normal images are compressed vertically, but 16:9 images can be reproduced in their original 16:9 aspect ratio with a video source which compress (squeezes) 16:9 images to 4:3 images. The register settings are the 16:9 CRT standard values. - 41 - CXA2150AQ 2) 16:9 CRT normal mode In this mode, 4:3 images are reproduced without modification. A black border appears at the left and right of the picture. In this mode, the H deflection size must be compressed by 25% compared to full mode. The CXA2150AQ performs compression with a register "EW_DC" that compresses the H size. Because excessive current flows to the horizontal deflection coil in this case, adequate consideration must be given to allowable power dissipation, etc., of the horizontal deflection coil in the design of the set. In addition, this concern can also be addressed through measures taken external to the IC, such as switching the horizontal deflection coil. Full mode should be used when performing memory processing and attaching a black border to the video signal. H blanking of the image normally uses the H-pulse input from HP_IN (Pin 39). However, the blanking width can be varied according to the control register setting when blanking is insufficient for the right and left black borders. The following three settings are added to the 16:9 CRT standard values for the register settings. HBLK_SW = 1 LEFT_BLK = Adjustment value RIGHT_BLK = Adjustment value The H angle of deflection also decreases, causing it to differ from the PIN compensation amount during H size full status. Therefore, in addition to the wide mode registers, "PIN_AMP" must also be readjusted only for this mode. 3) 16:9 CRT zoom mode In this mode, 4:3 images are reproduced by enlarging the picture without other modification. The top and bottom of normal 4:3 images are lost, but almost the entire picture can be reproduced for vista size video software, etc. which already has back borders at the top and bottom. The enlargement ratio can be controlled by the "V_ASPECT" register, and enlarging the picture by 33% compared to full mode allows zooming to be performed for 4:3 images without distortion. In this case, the number of scanning lines is reduced to 360 Iines compared to 480 Iines for full mode. The zooming position can be shifted vertically by the "V_SCROLL" register. V blanking of the image is performed by setting VBLK_SW = 0, and the top and bottom parts which are lost are also blanked during this mode. Adjust the following two registers with respect to the 16:9 CRT standard values for the register settings. V_ASPECT = 2Fh V_SCROLL = 1Fh or user control 4) 16:9 CRT subtitle-in mode When Cinema Scope Size images which have black borders at the top and bottom of the picture are merely enlarged with the zoom mode in 3) above, subtitles present in the black borders may be lost. Therefore, this mode is used to super-compress only the subtitle part and reproduce it on the display. Add the "LO_VLIN" adjustment to the zoom mode settings for the register settings. V_ASPECT = 2Fh V_SCROLL = 1Fh or user control LO_VLIN = Adjustment value - 42 - CXA2150AQ 5) 16:9 CRT two-picture mode This mode is used to reproduce two 4:3 video displays on a 16:9 CRT such as for P and P. The V size must be compressed to 67% in order to reproduce two displays on a 16:9 CRT without distortion using 480 scanning lines, and this can be set by "JMP_SW". By setting JMP_SW = 1, the V size is compressed except the period from the retrace of V_DRV signal to putting the reference pulses on R, G, B signal, and the AKB reference pulses remain in the over-scan position. The following timings can be adjusted with each register. The reference pulses: "AKBTIM" The end of the vertical blanking: "UP_BLK" The start of the vertical blanking: "LO_BLK" Adjust the following five registers with respect to the 16:9 CRT standard values for the register settings. JMP_SW = 1 AKBTIM = Adjustment value VBLK_SW = 1 UP_BLK = Adjustment value LO_BLK = Adjustment value 6) 16:9 CRT wide zoom mode This mode reproduces 4:3 video software on wide displays by enlarging 4:3 images without other modification and compressing the parts of the image which protrude from the picture into the top and bottom parts of the picture. The display enlargement ratio is controlled by V_ASPECT, and the compression ratios at the top and bottom of the picture are controlled by UP/LO_VLIN. Adjust the following three registers with respect to the 16:9 CRT standard values for the register settings. V_ASPECT = Adjustment value UP_VLIN = Adjustment value LO_VLIN = Adjustment value 7) 4:3 CRT normal mode This is the standard mode for 4:3 CRTs. The register settings are with respect to the 4:3 CRT standard values. 8) 4:3 CRT V compression mode This mode is used to reproduce M-N converter output consisting of 16:9 images expanded to 4:3 aspect ratio and other squeezed signals without distortion on a 4:3 CRT. In this case, the V size must be compressed to 75%. This is done using JMP_SW in 5) above. Fine adjustment of the V size is possible by adding the V_ASPECT adjustment. Adjust the following two registers with respect to the 4:3 CRT standard values for the register settings. V_ASPECT = Adjustment value JMP_SW =1 9) 4:3 CRT V compression mode for 100Hz TV (Flicker Free) The V deflection frequency for 100Hz TV sets is twice that 50Hz TV sets, so scanning may become rougher at the top of the picture when using the mode in 8) above. In this case, V compression is performed with V_ASPECT not using JMP_SW, and if necessary, the timings adding the reference pulse and the blanking period can be adjusted with AKBTIM and UP/LO_BLK in the same way as 5) above. Adjust the following five registers with respect to the 4:3 CRT standard values for the register settings. V_ASPECT = Adjustment value AKBTIM = Adjustment value VBLK_SW = 1 UP_BLK = Adjustment value LO_BLK = Adjustment value - 43 - CXA2150AQ Settings for Horizontal Deflection Frequency As regards horizontal deflection frequency, this IC corresponds to the following four point-scan modes. PS15K: Normal scan for NTSC/PAL/SECAM etc. PS31K: Double scan for NTSC etc., and VGA PS33K: HDTV 1080i and MUSE 1035i PS37K: SVGA PS45K: HDTV 720p See Table 1 for settings. 1) Settings for Pin 23 F0 and Pin 24 F1 L: Connect to GND M: Open the pin H: Connect to Pin 29 VREG5 2) Horizontal deflection (H_DRV) free-running frequency f0 PS15K: Point Scan 15.74kHz PS31K: Point Scan 31.5kHz PS33K: Point Scan 33.83kHz PS37K: Point Scan 37.9kHz PS45K: Point Scan 45kHz F1 L L L M M M H H H F0 L M H L M H L M H H_DRV f0 PS15K PS31K PS31K PS33K PS45K PS33K PS37K PS45K Storage Normal Normal Long Normal Normal Long Normal Long : Prohibited settings Table 1. Settings for Pin F0 and Pin F1 While switched by Pins F0 and F1, this IC changes horizontal deflection frequency of H_DRV output signal while H_DRV is high level, but doesn't have any other special sequences. Therefore it is recommended that a microcomputer be used in the TV set side for sequence control in the case of dynamic switching. - 44 - CXA2150AQ 3) Supported HOUT storage times The H_DRV signal output from Pin 40 is input to the horizontal deflection circuit of TV set to generate an H-pulse. This IC provides Normal mode and Long mode to support storage times from the rising edge of HD signal to the rising edge of H-pulse input to Pin 39 HP_IN. See Table 1 for settings Pins F0 and F1. CXA2150Q H-pulse HP_IN 39 Storage time H_DRV 40 HD signal H-deflection circuit HOUT To H-deflection block Fig. 1. Storage Time from HD to H-pulse The storage time differs slightly depending on the drive conditions of a TV set, etc. Fig. 2 shows examples of the range of the storage time covered for each mode. Conditions: "H_POSITION" and "AFC_BOW, ANGLE" etc. are center value, and the input H-pulse width is 4.5s. Assuming that an H-pulse width on a TV set is Tw [s], a converted value on Fig. 2, ST [s] is; ST = (4.5 - Tw) /2, ST < 0 (negative) : Shift to left, ST > 0 (positive) : Shift to right. In additions, the variable range for "H_POSITION" and "AFC_BOW, ANGLE" etc. are in Fig. 2. Storage time [s] Normal PS15K PS31K PS33K PS37K PS45K 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Long PS31K PS33K PS45K Fig. 2. Reference Example of Supported Storage Times for Each Mode (H-pulse Width: 4.5s) - 45 - CXA2150AQ Settings for Vertical Deflection Frequency The vertical deflection frequency is determined by combinations with settings made using pins F0 and F1 for horizontal deflection frequency and "VFREQ register" settings. See Table 2. In additions, Table 2 shows the regular number of lines for each set vertical frequency. Horizontal mode 0: 50Hz PS15K PS31K PS33K PS45K 312.5 625 675 x "VFREQ" register 1: 60Hz 262.5 525 562.5 750 2: 100Hz x 312.5 x x 3: 120Hz x 262.5 x x x: Prohibited settings Table 2. Settings for Vertical Deflection Frequency (Regular Number of Lines) for Each Horizontal Mode VSYNC signal input in the range from -50% to +12.5% of the regular number of lines is accepted. Therefore, when VSYNC is not input, the CXA2150AQ is free-running as the regular number of lines +12.5%. However, when input VSYNC frequency changes, the vertical picture size also changes because V_DRV output amplitude is Auto-Gain-Controlled depending on the regular number of lines. In addition, V_DRV output operates as interlaced or non interlaced mode depending on VSYNC input. SVGA Mode The CXA2150AQ can support the SVGA deflection frequencies (horizontal: 37.9kHz, vertical: 60Hz). The setting method is as follows: (See Table 1 PS37K.) Pin 23 (F0): Connected to Pin 29 (VREG5) (H) Pin 24 (F1): Open (M) "VFREQ" register: 1 The V_DRV output AGC operation in SVGA mode differs from other modes, so the "Settings for Vertical Deflection Frequency" above do not apply. Therefore, the vertical deflection free-running frequency fv is approximately 35Hz. In addition, VSYNC input up to fv (approximately 35Hz) is accepted, and even if the input VSYNC frequency changes within the AGC operating range, the vertical picture size does not change. - 46 - CXA2150AQ Vertical Timing Charts Figs. 3 to 12 show the vertical timing charts. Fig. 3: Relationship between "AKBTIM" and "UP/LO_BLK" variable ranges and various effective video line inputs Figs. 4 to 12 show each mode at 1125i (1080i). Fig. 4: Standard settings (VBLK_SW = 1, ZOOM_SW = 0, JUMP_SW = 0, V_ASPECT = 00h, ASP_SW = 0, RST_SW = 0, VDRV_SW = 0) Fig. 5: Zoom mode (VBLK_SW = 0, ZOOM_SW = 1, V_ASPECT = 2Fh) Fig. 6: JUMP (V compression) mode (JUMP_SW = 1) Fig. 7: Effective video ratio conversion mode (ASP_SW = 1) Fig. 8: (VDRV_SW = 1) Fig. 9: (RST_SW = 1) Fig. 10: When a faster VSYNC than the regular cycle is input such as when switching channels Fig. 11: When VSYNC input stops or when VSYNC is input suddenly Fig. 12: When VSYNC input stops or when VSYNC is input suddenly (RST_SW = 1) - 47 - Number of lines before and after VSYNC 30 15 10 5 0 5 10 15 20 25 30 35 40 45 50 25 20 55 VSYNC Bch-REFP variable range (AKBTIM = 0h to 1Fh: 10H to 41H/1H) 0H to 15H/1H before VSYNC BLK variable range at top of picture (UP_BLK = 0h to Fh: 0H to 30H/2H after Bch-REFP) 3 7 16 9 23 17 0H to 15H/1H after Bch-REFP VBLK range Equivalent to 480i Other than 480i 480i V effective video BLK variable range at bottom of picture (LO_BLK = 0h to Fh: 0H to 30H/2H before VSYNC) (NTSC 15.734kHz/60Hz, PAL 15.625kHz/50Hz, FF 31.25kHz/100Hz) Bch-REFP 95% effective video (Double speed 31.5kHz/60Hz) 960i V effective video 6 34 13 Bch-REFP 18 33 95% effective video 46 - 48 - 5 18 5 17 18 16 5 25 24 (MUSE 33.75kHz/60Hz) 1035i V effective video 40 14 39 53 Bch-REFP 95% effective video (DTV-HDTV 33.75kHz/60Hz) 1080i V effective video 14 30 Bch-REFP 95% effective video (DTV-HDTV 45kHz/60Hz) 720p V effective video 19 43 Bch-REFP 95% effective video 23 CXA2150AQ Fig. 3. Relationship between "AKBTIM" and "UP/LO_BLK" Variable Ranges and Various Effective Video Line Inputs 2nd field 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 **** 1st field Hsync Number of lines Vsync 1117 1118 1119 1120 1121 1122 1123 1124 1125 1 (554) (555) (556) (557) (558) (559) (560) (561) (562) Numbers in parentheses indicate the number of lines in the 2nd field. 0.75H VTIM SCP AKBTIM = 0 to 1F (7H to 38H) ROUT GOUT BOUT Approximately 100s UP_BLK = 0 to F (2H/step after the Bch reference pulse) (The VTIM fall is also linked.) VDRV+ Trace start point LO_BLK = 0 to F (-2H/step from VSYNC, 1125H to 1095H) (The VTIM rise is also linked.) (The SCP VBLK start is also linked.) - 49 - 1st field 558 559 560 561 562 563 2nd field Hsync 564 (1) 565 (2) 566 (3) 567 (4) 568 (5) 569 (6) 570 (7) 571 (8) 572 (9) 573 (10) 574 (11) 575 (12) 576 (13) 577 (14) 578 (15) 579 (16) 580 (17) **** (* * * *) Number of lines 554 555 556 557 Vsync 0.75H Numbers in parentheses indicate the number of lines in the 2nd field. VTIM SCP AKBTIM = 0 to 1F (7H to 38H) ROUT GOUT BOUT Approximately 100s UP_BLK = 0 to F (2H/step after the Bch reference pulse) (The VTIM fall is also linked.) Trace start point VDRV+ LO_BLK = 0 to F (-2H/step from VSYNC -0.5H, 562H to 532H) (The VTIM rise is also linked.) (The SCP VBLK start is also linked.) CXA2150AQ Fig. 4. V Timing Chart 1 - 1125i (1080i) Standard Settings 2nd field 2 Note: Linked according to the AKB_TIM value 3 4 5 6 7 8 9 10 11 12 **** **** Near line 80 **** **** **** 1st field Hsync Number of lines Vsync **** Near line 1054 * * * * 1122 1123 1124 1125 1 (Near line 490) (559) (560) (561) (562) Numbers in parentheses indicate the number of lines in the 2nd field. 0.75H VTIM SCP AKBTIM = 0 to 1F (7H to 38H) ROUT GOUT BOUT VDRV+ ZOOM amplitude ZOOM start point ZOOM cancel point - 50 - 1st field **** 559 560 561 562 563 2nd field **** Hsync 564 (1) 565 (2) 566 (3) 567 (4) 568 (5) 569 (6) 570 (7) 571 (8) 572 (9) 573 (10) 574 (11) * * * * Near line 642 * * * * * * * * * * * * (Near line 80) (* * * *) Note: Linked according to the AKB_TIM value Number of lines 0.75H **** Near line 490 Vsync Numbers in parentheses indicate the number of lines in the 2nd field. VTIM SCP AKBTIM = 0 to 1F (7H to 38H) ROUT GOUT BOUT VDRV+ ZOOM start point ZOOM amplitude ZOOM cancel point CXA2150AQ Fig. 5. V Timing Chart 2 - Zoom Mode (VBLK_SW = 0, ZOOM_SW = 1, V_ASPECT = 2Fh) 2nd field 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 **** 1st field Hsync Number of lines Vsync 1117 1118 1119 1120 1121 1122 1123 1124 1125 1 (554) (555) (556) (557) (558) (559) (560) (561) (562) Numbers in parentheses indicate the number of lines in the 2nd field. 0.75H VTIM SCP AKBTIM = 0 to 1F (7H to 38H) ROUT GOUT BOUT Approximately 100s The JUMP start timing is linked to AKBTIM. UP_BLK = 0 to F (2H/step after the Bch reference pulse) (The VTIM fall is also linked.) VDRV+ Trace start point Amplitude during JUMP LO_BLK = 0 to F (-2H/step from VSYNC, 1125H to 1095H) (The VTIM rise is also linked.) (The SCP VBLK start is also linked.) VDRV+ before JUMP The reference pulse stays in the top of the picture. - 51 - 1st field 558 559 560 561 562 563 2nd field Hsync 564 (1) 565 (2) 566 (3) 567 (4) 568 (5) 569 (6) 570 (7) 571 (8) 572 (9) 573 (10) 574 (11) 575 (12) 576 (13) 577 (14) 578 (15) 579 (16) 580 (17) **** (* * * *) Number of lines 554 555 556 557 Vsync 0.75H Numbers in parentheses indicate the number of lines in the 2nd field. VTIM SCP AKBTIM = 0 to 1F (7H to 38H) ROUT GOUT BOUT Approximately 100s The JUMP start timing is linked to AKBTIM. UP_BLK = 0 to F (2H/step after the Bch reference pulse) (The VTIM fall is also linked.) Trace start point Amplitude during JUMP The reference pulse stays in the top of the picture. LO_BLK = 0 to F (-2H/step from VSYNC -0.5H, 562H to 532H) (The VTIM rise is also linked.) (The SCP VBLK start is also linked.) VDRV+ before JUMP CXA2150AQ Fig. 6. V Timing Chart 3 - JUMP (V Compression) Mode (JUMP_SW = 1) 2nd field 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 **** 1st field Hsync Number of lines Vsync 1099 1100 1101 1102 1103 1104 * * * * 1124 1125 1 (536) (537) (538) (539) (540) (541) (561) (562) Numbers in parentheses indicate the number of lines in the 2nd field. 0.75H VTIM SCP AKBTIM = 0 to 1F (7H to 38H) ROUT GOUT 22H 22H ASPSW = 1 (BLK added until +22 lines after the Bch reference pulse) UP_BLK = 0 to F (2H/step from Bch reference pulse + 22 lines) (The VTIM fall is also linked.) BOUT VDRV+ 100% Trace start point VDP+ of ASPSW = 0 110% ASPSW = 1 LO_BLK = 0 to F (BLK added until 22 lines before VSYNC) Approximately 100s (-2H/step from -22 lines, 1125H to 1095H) (The VTIM rise is also linked.) (The SCP VBLK start is also linked.) - 52 - 1st field 540 541 **** 561 562 563 2nd field Hsync 564 (1) 565 (2) 566 (3) 567 (4) 568 (5) 569 (6) 570 (7) 571 (8) 572 (9) 573 (10) 574 (11) 575 (12) 576 (13) 577 (14) 578 (15) 579 (16) 580 (17) **** (* * * *) Number of lines 0.75H 536 537 538 539 Vsync Numbers in parentheses indicate the number of lines in the 2nd field. VTIM SCP AKBTIM = 0 to 1F (7H to 38H) ROUT GOUT 22H 22H UP_BLK = 0 to F (2H/step from Bch reference pulse +22 lines) (The VTIM fall is also linked.) ASPSW = 1 (BLK added until +22 lines after the Bch reference pulse) 100% 110% BOUT VDRV+ ASPSW = 1 LO_BLK = 0 to F (BLK added until 22 lines before VSYNC) Approximately 100s (-2H/step from VSYNC -22.5H, 562H to 532H) (The VTIM rise is also linked.) (The SCP VBLK start is also linked.) Trace start point CXA2150AQ VDP+ of ASPSW = 0 Fig. 7. V Timing Chart 4 - Effective Video Ratio Conversion Mode (ASP_SW = 1) 2nd field 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 **** 1st field Hsync Number of lines Vsync 1117 1118 1119 1120 1121 1122 1123 1124 1125 1 (554) (555) (556) (557) (558) (559) (560) (561) (562) Numbers in parentheses indicate the number of lines in the 2nd field. 0.75H VTIM SCP AKBTIM = 0 to 1F (7H to 38H) ROUT GOUT BOUT Approximately 100s The VDRV_SW end start timing is linked to AKBTIM. UP_BLK = 0 to F (2H/step after the Bch reference pulse) (The VTIM fall is also linked.) VDRV+ Trace start point Amplitude when VDRV_SW = 1 LO_BLK = 0 to F (-2H/step from VSYNC, 1125H to 1095H) (The VTIM rise is also linked.) (The SCP VBLK start is also linked.) The reference pulse jumps to the top of the picture. - 53 - 1st field 558 559 560 561 562 563 2nd field Hsync 564 (1) 565 (2) 566 (3) 567 (4) 568 (5) 569 (6) 570 (7) 571 (8) 572 (9) 573 (10) 574 (11) 575 (12) 576 (13) 577 (14) 578 (15) 579 (16) 580 (17) **** (* * * *) Number of lines 554 555 556 557 Vsync 0.75H Numbers in parentheses indicate the number of lines in the 2nd field. VTIM SCP AKBTIM = 0 to 1F (7H to 38H) ROUT GOUT BOUT Approximately 100s The VDRV_SW end start timing is linked to AKBTIM. UP_BLK = 0 to F (2H/step after the Bch reference pulse) (The VTIM fall is also linked.) Trace start point Amplitude when VDRV_SW = 1 The reference pulse jumps to the top of the picture. VDRV+ LO_BLK = 0 to F (-2H/step from VSYNC -0.5H, 562H to 532H) (The VTIM rise is also linked.) (The SCP VBLK start is also linked.) CXA2150AQ Fig. 8. V Timing Chart 5 - VDRV_SW = 1 2nd field 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 **** 1st field Hsync Number of lines Vsync * * * * * * * * 1119 1120 1121 1122 1123 1124 1125 1 (556) (557) (558) (559) (560) (561) (562) Numbers in parentheses indicate the number of lines in the 2nd field. 0.75H VTIM SCP AKBTIM = 0 to 1F (7H to 38H) ROUT GOUT BOUT UP_BLK = 0 to F (2H/step after the Bch reference pulse) (The VTIM fall is also linked.) LO_BLK = 0 to F (-2H/step from VSYNC, 1125H to 1095H), (The VTIM rise is also linked.) (The SCP VBLK start is also linked.) 6.25H before VSYNC + 0.75H VDRV+ Trace start point - 54 - 1st field 558 559 560 561 562 563 2nd field Hsync 564 (1) 565 (2) 566 (3) 567 (4) 568 (5) 569 (6) 570 (7) 571 (8) 572 (9) 573 (10) 574 (11) 575 (12) 576 (13) 577 (14) 578 (15) 579 (16) 580 (17) **** (* * * *) Number of lines **** **** 556 557 Vsync 0.75H Numbers in parentheses indicate the number of lines in the 2nd field. VTIM SCP AKBTIM = 0 to 1F (7H to 38H) ROUT GOUT BOUT UP_BLK = 0 to F (2H/step after the Bch reference pulse) (The VTIM fall is also linked.) LO_BLK = 0 to F (-2H/step from VSYNC, 1125H to 1095H), (The VTIM rise is also linked.) (The SCP VBLK start is also linked.) 6.25H before VSYNC + 0.75H VDRV+ Trace start point CXA2150AQ Fig. 9. V Timing Chart 6 - RST_SW = 1 1V 1/2V mask 1/2V mask 1/2V mask 1/2V mask 1V 1V 1/2V mask Vsync Ignored Ignored VDRV+ - 55 - VTIM ROUT GOUT BOUT VSYNC is not accepted within a 1/2V period from the start of the VDRV+ retrace. (1/2V mask) When a shorter V than the normal V frequency is input, the RGBOUT V blanking starts at approximately the same time as VSYNC, regardless of the LO_BLK data. CXA2150AQ Fig. 10. V Timing Chart 7 - When a faster VSYNC than the regular cycle is input such as when switching channels No_Vsync 1V 1V Ignored 1V Vsync 1V 1/8V 1/8V 1/8V 1V 1/2V Internal retrace pulse VDRV+ - 56 - VTIM ROUT GOUT BOUT When VSYNC input stops, free-running at a 1V + 1/8V cycle results. CXA2150AQ Fig. 11. V Timing Chart 8 - When VSYNC input stops or when VSYNC is input suddenly No_Vsync 1V 1V Ignored 1V Vsync 6.25H 1/8V 1/8V 1/8V 7H 1V 6.25H 1V 6.25H 1/2V 0.75H 6.25H 0.75H 6.25H 0.75H Internal retrace pulse 7H 6.25H 0.75H 7H - 57 - A B VDRV+ C A A) When VSYNC is input: VDP+ retrace starts from 6.25H before VSYNC. B) When VSYNC input stops: Free-running at a 1/8V + 1V cycle results. C) When VSYNC is input suddenly: VDRV+ retrace starts with precedence on the VSYNC 1/2V or more after the trace start or the internal retrace pulse 6.25H before 1V is reached, whichever is input first. CXA2150AQ Fig. 12. Timing Chart 9 - When VSYNC input stops or when VSYNC is input suddenly (RST_SW = 1) CXA2150AQ Horizontal System Timing Chart HSYNC center Ref.0% (100%: 1H) HS_IN Pin 28 Recommended HSYNC width : 1s or more Y_IN Pin 20 H_POSITION: Phpos [%] HP_IN Pin 39 H pulse center CLP_PHASE CLP_SHIFT : Pclp [%] 1 Clamp pulse width: Fixed to 4% SCP Pin 27 RIGHT_BLK : Prblk [%] LEFT_BLK : Plblk [%] 2 R, G, B_OUT Pins 64, 63, 62 HBLK period 1 When "CLP_GATE" =1, the Clamp pulse is masked in the period that input HSYNC is high level. The internal clamp pulse is same, so set to a suitable clamped phase using "CLP_PHASE" and "CLP_SHIFT". 2 When "HBLK_SW" =1, the HBLK period on R, G, B_OUT and SCP is made by processing the pulse set by "RIGHT, LEFT_BLK" and the period that H-pulse is high level with OR logic. When "HBLK_SW" = 0, the HBLK is the period that H-pulse is high level. Fig. 13 - 58 - CXA2150AQ V Protect Pin 35 (VPROT) is used to completely blanks the R, G, B_OUT output during abnormal signal input by feeding back the vertical deflection drive signal using V_DRV output. (Reference pulses are also blanked.) The conditions for determining whether the VPROT input is "normal input" are as follows. (1) The input signal should rise to 1.05V or more after VSYNC (2) The bottom edge of the input signal should fall to 0.75V or less after (1) above If a signal that do not satisfy both (1) and (2) above continues for more than 3 V cycles, it is considered "abnormal input" and R, G, B_OUT are completely blanked. If the input returns to "normal input", the blanking will be cancelled from the next V cycle. In addition R, G, B_OUT are also completely blanked during power-on and when "V_ON" = 0 (V_DRV signal is just DC with no amplitude.). DC voltage 1.05V 0.75V Normal input to VPROT input pin DC voltage DC voltage 1.05V 1.05V 0.75V 0.75V Abnormal input to VPROT input pin example 1 (The top edge of the input signal does not rise to 1.05V or more.) Abnormal input to VPROT input pin example 2 (The bottom edge of the input signal does not fall to 0.75V or less.) Fig. 14. Signal Input Status to VPROT - 59 - CXA2150AQ Frequency Response Related Settings Table 3 shows the center frequency f0 setting value reference data for each control register related to frequency response. Function Center frequency f0 [MHz] by mode ("SYSTEM") Corresponding "SHP_F0" "VM_F0" register NORMAL (0) FF (1) HD (2) DTV (3) "SHARPNESS" 0 1 0 1 0 1 0 1 0 1 0 1 VM output "VM_LEV" 0 1 0 1 0 0 1 1 2 2 3.0 4.0 4.0 5.4 1.7 2.3 2.0 2.7 0.9 1.2 2.0 2.7 2.4 3.2 3.0 4.0 6.0 8.1 7.9 10.8 3.4 4.6 4.0 5.4 1.7 2.3 4.0 5.4 4.8 6.5 6.0 8.1 11.9 16.1 23.8 32.3 4.8 6.5 6.0 8.1 3.4 4.6 6.0 8.1 7.9 10.8 11.9 16.1 17.9 24.2 35.7 48.4 7.1 9.7 8.9 12.1 5.1 6.9 8.9 12.1 11.9 16.1 17.9 24.2 Main sharpness High f0 sharpness Color dependent sharpness LTI "SHP_F1" "SHP_CD" "LTI_LEV" CTI "CTI_LEV" Table 3. Center Frequency f0 Reference Values by Function - 60 - CXA2150AQ LTI/CTI Mode The LTI/CTI function improves the input Y/CbCr signal slew rate. The center frequency f0 changes according to registers "SYSTEM" and "SHP_F0". (See Table 3 on page 60.) In addition, this f0 determines the optimum input slew rate t0 for LTI/CTI. t0 = 1/(2f0) The LTI/CTI improvement mode can be changed by "LTI_MODE" and "CTI_MODE". When a signal with the optimum input slew rate t0 for LTI/CTI is input: 0 = Normal mode (Black/white both-side improvement) The edges are corrected centering on a slew rate of 50%. 1 = Black side improvement mode The minus side from 50% is improved, and the slew rate is half from the original waveform. 2 = White side improvement mode The plus side from 50% is improved, and the slew rate is half from the original waveform. See Fig. 15 for a description of the principle. 100% 100% 50% 50% [Input] 0% 50% 100% 0% 0% [Output] Normal mode Black side improvement mode White side improvement mode Fig. 15. Description of LTI/CTI Mode Principle - 61 - CXA2150AQ PRE_RGB Output The PRE_RGB signal with the three R, G and B channels which have passed through the gamma circuit added is output to Pin 60 (PRE_RGB). (See Fig. 16.) Internal R, G and B signals GAMMA DRIVE To R, G and B outputs fc: 2.4MHz LPF BLK AMP 60 PRE_RGB output H, VBLK 100 IRE (PICTURE: Max) R signal G signal B signal Internal H, VBLK PRE_RGB output At RGB 100 IRE input: 1.35Vp-p Black level: 1.5V 225mV (BRIGHT: Min/Max) Blanking period: replaced with black level Fig. 16. Overview of PRE_RGB Output The horizontal and vertical blanking periods are replaced with the black level(when there is no RGB input.). Also, the output DC level is linked to "BRIGHT" and "SUB_BRIGHT". Passing the PRE_RGB output through an appropriate external LPF and inputting it to Pin 59 (SABL_IN) is effective for the short-loop RGB gain correction. Returning the PRE_RGB output to Pin 38 (L2_FIL) is also effective for AFC compensation using the RGB signal. - 62 - CXA2150AQ AKBOFF Mode The CXA2150AQ also supports sets that do not use the AKB system. (AKBOFF mode) AKBOFF mode is established by setting the register "AKBOFF" to 1. * The R, G and B output DC levels are adjusted by "R, G, B_CUTOFF", respectively. * The AKB reference pulse (REF-P) is not added to the R, G and B outputs. * Connect Pin 58 (IK_IN) to GND via a capacitor. * Two different DC levels can be selected for the R, G and B output horizontal and vertical blanking periods by "BLK_OFF". * Like AKB mode, the HBLK period is set by "L/R_BLK" and the VBLK period is set by "AKBTIM" and "UP/LO_BLK". Fig. 17 shows the RGB blanking in AKBOFF mode. 1) BLK_OFF = 0 * VBLK period level: Fixed at approximately 0.4 V * HBLK period level: R, G and B are controlled together by "BLK_BTM". * "BRIGHT" and "SUB_BRIGHT": Control only the effective video (non-blanking) period together for R, G and B. * "R, G, B_CUTOFF": Control only the effective video period independently for R, G and B, respectively. 2) BLK_OFF = 1 * VBLK and HBLK period levels: Approximately 8 IRE (reference pulse level) when "BRIGHT" and "SUB_BRIGHT" are set to center. * "BRIGHT" and "SUB_BRIGHT": Control only the effective video (non-blanking) period together for R, G and B. * "R, G, B_CUTOFF": Control the entire period independently for R, G and B, respectively Input Y signal HBLK period Internal CBLK (composite blanking) VBLK period "BLK_OFF" = 0 B_OUT Approximately 0.4V Varied by "BLK_BTM" "BLK_OFF" = 1 B_OUT Approximately 8 IRE Fig. 17. RGB Blanking Period in AKBOFF Mode - 63 - CXA2150AQ Signal Processing The CXA2150AQ consists of Y, color difference (Cb/Cr), RGB, horizontal deflection, and vertical deflection signal processing. All these types of signal processing are controlled by I2C bus. 1. Y signal processing A 0.7Vp-p (100 IRE) Y signal is input to Pin 20 (Y_IN) via a capacitor. This Y signal is input-clamped and passed through sharpness control, luminance transient improvement (LTI), DC transmission rate correction, and the auto pedestal circuits. It is then output to the MATRIX circuit. The Y signal's differential wave (VM signal) is output to Pin 14 (VM_OUT) with positive polarity. The center frequency for sharpness (f0), LTI, and VM, along with the Y signal frequency response, change according to the "SYSTEM" and "SHP_F0" registers. (See Table 3 on page 60.) The CXA2150AQ provides the following three types of sharpness features: a) Main sharpness The "SHARPNESS" register can be used to control the sharpness gain, while the "PRE/OVER" register can be used to control the pre-shoot/over-shoot ratio. b) High f0 sharpness "SHP_F1" can be used to control the sharpness gain at the higher center frequency level f1. This is useful for improving the high-frequency attenuation of a digital IC at the previous stage. c) Color-dependent (CD) sharpness The Y signal's low frequency is enhanced according to the Cr signal level only while the Cr input signal is positive. "SHP_CD" can be used to control the enhancement gain. "CD_OFF" can be used to turn off this feature. This feature is useful for enhancing the brightness change of the red elements on the screen. The LTI generates contour correction signals at the Y signal's rising and falling edges and achieves contour enhancement by adding the correction signal to the original signal. "LTI_LEV" can be used to change the enhancement gain, and "LTI_MODE" can be used to change the improvement mode. Pin 13 (YF_OFF) can achieve high-speed MUTE on the VM signal, sharpness feature, and color signal. See the pin description. The VM signal's output amplitude can be modulated by applying voltage to Pin 15 (VM_MOD). Both pins can be used as parameters for image-quality control. There are five control registers for the VM signal: "VM_LEV" : VM output gain control "VM_F0" : The VM signal's center frequency control during differentiation "VM_DLY" : Control of the phase difference between the VM signal and the output RGB signal "VM_COR" : Coring level control for improving the VM signal's S/N "VM_LMT" : The VM signal's dynamic range control based on the internal limiter level - 64 - CXA2150AQ The "DC_TRAN" register can be used to adjust the DC transmission rate between 103% and 80% by detecting the input signal's APL. A change of brightness caused by the input Y signal's DC offset can be reduced by "Y_OFFSET". Auto pedestal is a black-level correction circuit that detects the black elements in an input signal and automatically pulls any part below the specified level to the pedestal level. The point of inflection can be adjusted using the "DPIC_LEV" register. In addition, Pin 12 (DPDT_OFF) stops the operation of the automatic pedestal circuit and the signal interval detection that is used to control the DC transmission rate. For details, see the pin description. This IC is equipped with two registers that can be used for aging on the production line: "AGING_W": Full white output "AGING_B": Full black output 2. Color difference (CbCr) signal processing Cb/Cr color difference signals with 0.7Vp-p (100 IRE) are input to Pins 21 (CB_IN) and 22 (CR_IN) via a capacitor. The Cb/Cr signal is input-clamped and passed through chrominance transient improvement (CTI), HUE control, color control, and the detection axis setting circuit. It is then output to the MATRIX circuit. Similar to the LTI, the CTI generates contour-correction signals at the color difference signal's rising and falling edges and achieves contour enhancement by adding the correction signal to the original signal. "CTI_LEV" can be used to change the enhancement gain, while "CTI_MODE" can be used to change the improvement mode. The central frequency for CTI changes according to "SYSTEM" and "SHP_F0". (See Table 3 on page 60.) With the color gain control amplifier, setting "COLOR" data to "00h" results in color-off mode. Pin 13 (YF_OFF) can also be used to turn the color off. See the pin description. The detection axis setting circuit sets the angles of the R-Y and G-Y axes and their weighting factor with the B-Y axis fixed. "COL_AXIS" can set four angles and weighting factors, so that an appropriate setting can be selected according to the destination. The signal is converted to three different color signals (R-Y, G-Y, and B-Y) by the AXIS circuit, and then input to the MATRIX circuit along with the Y signal to obtain the RGB primary colors. 3. RGB signal processing The RGB signals are output after passing through YSYM1, white balance switching, picture control, subcontrast control, bright/sub-bright control, YSYM2, amplitude limiter, dynamic color, gamma correction, drive control, cut-off control, and H and V blanking circuits. Pin 7 (YSYM1) either tones down the main signal to about 1/3 (YM) or switches it to the RGB1 analog input signal, (YS). Apply a control signal to this pin. See the pin description. The signal output from the YSYM1 circuit enters the white balance SW, where the R-G-B balance can be changed by "WB_SW". The picture control has a variable range of about 13dB. The sub-contrast control has a variable range of about -0.9 to +1.2 dB. The bright/sub-bright control has a variable range of 14 IRE. - 65 - CXA2150AQ Pin 2 (YSYM2) either tones down the main signal or the RGB1 analog signal to about 1/3 (YM) or switches it to the RGB2 analog input signal, (YS). Apply a control signal to this pin. See the pin description. The RGB2 analog signal can be controlled by brightness including ABL, but picture control and white balance SW have no effect. "LRGB2_LEV" can be used to independently adjust the amplitude. The amplitude limiter is activated when the input signal's amplitude is too high. "PLIMIT_LEV" is used to select the desired input amplitude level at which the limiter is to be activated. This can be used to protect TV sets against excessive input. The signal obtained is then passed through dynamic color, gamma correction, and drive control (RGB independently adjustable), placed under the AKB system's cut-off control, and then output via a buffer. If 75% of the R-signal level is less than G or B, the dynamic color controls the gain of R and B to increase the picture's color density. "DCOL" can be used to change this effect. Furthermore, this IC is equipped with a built-in peak ABL. It limits the peak video signal by detecting the RGB output signal's peak level and then reducing the picture gain. The detection voltage can be changed by "P_ABL". Select an appropriate feedback time constant by forming an external LPF using Pin 11 (PABL_FIL). To Pin 56 (ABL_IN), input a voltage, which represents the anode current via an external LPF with a range of 0 to 5V. The voltage applied to ABL_IN is compared with three internal reference voltage values and then is charged/discharged by the capacitor connected to Pin 57 (ABL_FIL). "ABL_TH" can be used to change the internal reference voltage. The effect of ABL on the RGB signal corresponds to the voltage on the ABL_FIL pin. (See the curve data.) The ABL feature includes picture ABL for suppressing the RGB signal's amplitude and brightness ABL for reducing the DC level; the desired mode can be set using "ABL_MODE". At Pin 60 (PRE_RGB), a PRE_RGB signal, which is obtained by mixing the signals from three channels (R, G and B) after the gamma correction circuit, is output via LPF (fc: 2.4MHz). This PRE_RGB signal is useful for AFC correction by the RGB signal if it is fed back to Pin 38 (L2_FIL) via an appropriate external LPF. The ABL feature is also applicable to the voltage that is applied to Pin 59 (SABL_IN), in which case its effects can be adjusted using "S_ABL". This is useful for ABL correction with a short loop, if the PRE_RGB signal is input to SABL_IN via an appropriate external LPF. At the output stage, "BLK_BTM" can be used to set the voltage at the H blanking section. This voltage is defined as the voltage difference from AKB's reference-pulse DC. Therefore, the absolute voltage value varies from R to G to B according to the status of AKB, but is not affected by the setting of DC level controls such as brightness. The AKB system (auto cut-off feature) automatically adjusts bias on the cut-off side by forming a loop between the CRT and this IC. This loop can also compensate for the CRT's change over its lifetime. This system adjusts color density using "R, G, B_DRV" for adjusting gain between RGB outputs with the I2C bus and "R, G, B_CUTOFF" for adjusting the DC level while AKB is active. - 66 - CXA2150AQ AKB operation is described as follows. (For the timing chart of reference-pulse output, see Fig. 3 on page 48.) * On the upper part of the screen (overscan section), the reference pulses for AKB are output in the order of RGB by shifting one line at a level of 8 IRE. * Detects the cathode current generated by each reference pulse that was output, converts it to a voltage, then inputs it as IK to Pin 58 (IK_IN) via a capacitor. Because this IK signal is input-clamped, be sure to input the signal at a stable level during V blanking, immediately before the reference pulse. * Compares the IK_IN input voltage with the IC's internal reference voltage and samples the signal by charging/discharging it, using an internal capacitor, at each reference pulse interval for R, G and B. This process is inhibited beyond the reference pulse interval. * Changes the DC level of R, G, B_OUT according to the internal capacitor's voltage. This is repeated for each field until the clamped IK signal's voltage at each reference pulse interval for R, G and B becomes equal to the IC's internal reference voltage. The reference voltage is provided for each instance of R, G and B and can be changed by "R, G, B_CUTOFF". When the set's power is turned on, the IK signal's reference pulse voltage remains low until the cathode is warmed up. Therefore, the internal capacitor's voltage is set to the maximum level, and R, G, B_OUT's DC level is set to the maximum value. When the cathode is warmed up and the IK signal's level rises, the internal capacitor's voltage starts falling from its maximum level, and R, G, B_OUT's DC level also starts falling. The AKB loop then becomes stable and converges. The CXA2150AQ returns a value of "1" to the "IKR" status register when the levels of all R, G and B internal capacitors drop below the specified maximum level. When the CXA2150AQ's power is turned on, the internal capacitors' voltage starts from the GND level; therefore, "1" may be returned to IKR before the AKB loop converges. Mask reading of the "IKR" status register for an appropriate length of time after powering up this IC. This IC provides an AKBOFF (manual cut-off) mode. When the "AKBOFF" register is set to 1, R, G, B_OUT's DC level is controlled by "R, G, B_CUTOFF". In this case, drop Pin 58 (IK_IN) to GND with a capacitor. The "BLK_OFF" register takes effect only in the AKBOFF mode. When BLK_OFF = 0, H and V blanking are applied to the RGB signals. When BLK_OFF = 1, the H and V blanking intervals for the RGB signal are output at a level of +8 IRE. 4. Horizontal deflection signal processing 1) H sync input A positive polarity horizontal synchronizing signal with about 5Vp-p is input to Pin 26 (HS_IN) using DC coupling or AC coupling with a capacitor. For the phase and width of input H sync, see Fig. 13 on page 58. For the CXA2150AQ, inputting continuous H sync is recommended during V intervals, so it is also recommended that PLL exists at the previous stage. 2) AFC 1st loop The CXA2150AQ employs a VCO that uses a ceramic oscillator in the horizontal oscillator circuit (fc: 2.696874MHz). Its division value is determined by the settings of Pins 23 (F0) and 24 (F1) to support five different horizontal deflection frequencies fH. (fH: 15.7, 31.5, 33.75, 37.9, or 45kHz; see Table 1 on page 44.) The AFC 1st loop is obtained by comparing the phase of the input H sync with the phase of the internal H reference pulse (HREF1), which is obtained by dividing the 2.7MHz-VCO output. The "SYNC_PHASE" register can be used to shift to the phase of HREF1. This is useful when a Y signal's phase is delayed compared to the H sync signal at the previous stage. - 67 - CXA2150AQ The 1st loop's response characteristics are set using the lag lead filter constant at Pin 32 (AFC_FIL) and the "AFC_MODE" register. If AFC is locked with input H sync, a value of "1" is output to the "HLOCK" status register, and the result of the comparison of internal free-running frequency and input frequency is output to "HCENT". This status is useful for detecting an input signal. "CLP_PHASE" and "CLP_SHIFT" can be used to control the phases of CXA2150AQ's internal clamp pulse and the clamp pulse superimposed on SCP output at Pin 27. "CLP_GATE" can be used to set whether or not to gate the clamp pulse during the input H sync's High period. 3) AFC 2nd loop The AFC 2nd loop is obtained by comparing the phase of the reference H pulse derived from the 1st loop (HREF2) with the phase of the horizontal deflection pulse input to Pin 39 (HP_IN) (H pulse) to control the phase of H_DRV output (Pin 40). "H_POSITION" can be used to adjust the phase of HREF2. In other words, it is used to control the horizontal position of the video image that is displayed on the CRT. Additionally, "AFC_BOW, ANGLE" are used to correct the distortion of vertical lines by superimposing a correction signal derived from the V-shaped saw-tooth wave. The high voltage fluctuations correction signal that is input to Pin 35 (HCOMP_IN) can be used to correct high voltage fluctuations in the horizontal direction. The amount of correction can be changed by using "AFC_COMP". For the delay between the H_DRV signal and H pulse generation, that is, the HOUT storage time, this IC provides two different modes that can be set using pins 23 (F0) and 24 (F1). (See Table 1 on page 44.) The H pulse input to Pin 39 (HP_IN) is used for horizontal blanking, which is superimposed on the R, G, B and SCP output. When HBLK_SW = 1, "L, R_BLK" can be used to control horizontal blanking on the screen for R, G, B outputs and the horizontal blanking pulse that is superimposed on SCP output. Since H_DRV output is an open collector connect a resistor of about 2.7k to VCC9. Additionally, limit the high voltage to 5V by connecting a 3.3k resistor to GND to protect the H_DRV output from over voltage. H_DRV output is equipped with start/stop features at the time of power ON/OFF. These features are activated automatically. When Pin 29's VREG5 terminal voltage is about 4V or lower, H_DRV is off and its output is fixed at the High level. Furthermore, to protect the TV set, the input pin HPROT (Pin 34) is provided to stop horizontal deflection. If a voltage of about 2V is applied to Pin 34 (HPROT) for more than seven V cycles, H_DRV output is set to off (High level) and RGB output is totally blanked. In this case, a value of "1" is output to the "HNG" status register. To reset this status, power down the IC once and then start it up again. 5. Vertical deflection signal processing 1) V sync input A positive polarity vertical synchronizing signal with about 5Vp-p is input to Pin 42 (VS_IN). (The High period must be at least 3H.) An internal V sync is generated from input V sync using its rising edge as a trigger. Therefore, the input V sync's rising phase is important. There must be no H sync, equivalent pulse, or instability, because sync separation is assumed to be completed on the input V sync at the previous stage of this IC. - 68 - CXA2150AQ 2) Vertical synchronization processing The mode of the interval V countdown system is determined by the horizontal deflection frequency (fH) settings at pins F0 and F1 and the "VFREQ" register. (See Table 2 on page 46.) The number of lines defined by fH setting are loaded to operate the UP & DOWN counter. The counter is reset at the rising edge of the input V sync. Note that V sync detection is masked for a period equivalent to approximately 1/2 the regular lines in order to reject continuous noise during channel change. When V sync input doesn't exist, internal V sync becomes free running at about +12.5% more lines than regular. In other words the V countdown system's pulling range is about -50% to +12.5% of regular lines. Synchronized to internal V sync, various timing pulses are generated: * VOSC reset pulse The vertical deflection retracing timing can be changed with respect to the video signal by switching the VOSC reset timing before or after V sync using "RST_SW". * Sampling pulse for the VAGC circuit * R, G and B references pulse for AKB "AKBTIM" is used to set the reference pulse timing. The pulse generated is sent to the RGB signal processing section, where it is superimposed on the RGB signals. * V blanking pulse The time from internal VSYNC to the Bch reference pulse is the reference V blanking interval. "UP, LO_BLK" can be used to increase the vertical blanking interval on the screen. The V blanking pulse is not only sent to the RGB signal processing section but also output as a VTIM signal at Pin 54 (VTIM). * Clamp pulse for IK input and V blanking pulse for SCP The pulse from the beginning of V blanking up to the Rch reference pulse is used as the clamp pulse for the IK input signal and as the V blanking pulse that is superimposed on SCP output. 3) VOSC (oscillator) section This IC employs an AGC circuit for VOSC. The AGC circuit suppresses unnecessary transient responses that may occur during channel change. The reference SAW waveform is derived by charge/discharge of the capacitance connected to Pin 48 (V_OSC). This reference SAW signal is compared with the internal reference voltage at the time of the sampling pulse, and AGC is activated by controlling the voltage of the capacitance connected to Pin 49 (V_AGC). To prevent sag on the V retrace rising edge, the V_OSC (Pin 48) capacitor should use a material (such as polypropylene) with low internal resistance. 4) Wide-mode support block The reference SAW signal generated at VOSC is input to the wide-mode block. In this block, control is provided for the wide modes "V_ASPECT", "V_SCROLL", "UP, LO_VLIN", "JMP_SW", and "ZOOM_SW". When ZOOM_SW = 1, the SAW signal adjusted by "V_ASPECT", etc., is limited vertically, in which case the setting VBLK_SW = 0 adds the limited interval to V blanking. During zoom mode, the OSD display position should be controlled by the microcomputer without using the VTIM signal. When ASP_SW = 1, the amplitude of the V_DRV output signal increases by about 10%, and 22 lines of V blanking are added at the top and bottom of the screen. This feature is useful for stretching the source when there are not enough valid video lines. The SAW signal output from the wide-mode block is input to the block that forms each V output signal. Therefore, all V system output signals are handled in wide mode. - 69 - CXA2150AQ 5) Various V system output signals The V_DRV- and V_DRV+ signals are output to Pins 52 and 53, respectively. These signals are used as the vertical deflection signal. At first power on, "V_ON" is preset to "0"; so V_DRV+ and V_DRV- are DC output. The VSAW waveform is not output until "1" is written to the control register. It is recommended to write "1" after degaussing is complete. Adjustments available for the V_DRV signal include: "V_SIZE", "V_POSITION", "V_LIN", and "S_CORRECTION". "VDRV_SW" increases the V_DRV signal level by about 5% in the interval up to the Bch reference pulse. Its purpose is to physically separate the reference pulse away from the video signal. The high voltage fluctuation correction signal that is input to Pin 37 (VCOMP_IN) can be used to correct high voltage fluctuation of the vertical picture size. The amount of correction can be changed using "V_COMP". At Pin 47 (EW_DRV), a parabolic wave with a cycle of V is output. This is used to correct the horizontal picture size and pin distortion. Available adjustments are: "H_SIZE", "PIN_AMP", "PIN_PHASE", "UP, LO_CPIN", and "UP, LO_UCG, UCP". The high voltage fluctuation correction signal input to Pin 36 (HCOMP_IN) can be used to correct high voltage fluctuation of the horizontal picture size and pin distortion. The amount of correction can be changed using "H_COMP" and "PIN_COMP". VSAW0 and VSAW1 at Pins 50 and 51 are the V-shaped, saw-tooth waves that allow DC level and amplitude to be controlled independently. They are useful for vertical pin distortion correction circuits, picture rotation (horizontal trapezoidal distortion) correction circuits, etc. At Pin 46 (DF_PARA), a parabolic wave with a cycle of V is output. This can be used to modulate the amplitude of the dynamic focus voltage at a vertical cycle. At Pin 43 (HC_PARA), a parabolic wave with a cycle of V is output. This can control DC level and the SAW element's amplitude and parabolic amplitude. It is useful for correcting the asynchronous element of the raster position and raster distortion. At Pin 45 (MP_PARA), a parabolic wave with a cycle of V is output. This can control the DC level and parabolic amplitude. It is useful for a PWM circuit that switches an S-shaped capacitor during a trace interval to control horizontal linearity. Furthermore, a VPROT input pin (Pin 35) is provided to forcibly turn off RGB output in the event of a V deflection error on the TV set. If input to Pin 35 (VPROT) remains erroneous for more than three V cycles, RGB output is totally blanked. In this case, a value of "1" is written in the "VNG" status register. For the input conditions, see Fig. 14 on page 59. - 70 - CXA2150AQ Notes on Operation * Because the R, G and B signals output from the CXA2150AQ are DC direct connected, the pattern (set board) must be designed with consideration given to minimizing interface from around the power supply and GND. Do not separate the GND patterns for each pin. A solid earth is ideal. Design the power supply as low impedance as possible. Locate the by-pass capacitor which is inserted between the power supply and GND as near to the pin as possible. Also, it is recommended that buffers be connected to R, G and B_OUT as close to the IC as possible. * Input the Y/Cb/Cr and R/G/B signals at a sufficiently low impedance, as these inputs are clamped by the capacitors connected to the pins. * The 5V regulator is formed by connecting a NPN-Tr between Pin 29 (VREG5) and Pin 30 (VBIAS). The regulator is for controlling the relation between rising and falling of VCC9 supply and of VREG5 voltage that is a CXA2150AQ's horizontal supply. Locate the NPN-Tr and by-pass capacitors as close to the pins as possible. When 5V is supplied to the VREG5 pin from an external source, separate from the signal system power supply VCC5 and open Pin 30 (VBIAS). Notes for each pin are shown in Table 4. - 71 - CXA2150AQ Pin Pin name No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 GND_OUT YSYM2 GND_SIG B2_IN G2_IN R2_IN YSYM1 B1_IN G1_IN R1_IN PABL_FIL Notes on operation and processing when unused Design as solid a pattern as possible, and be common to Pin 3 (GND_SIG). Unused, connect to GND. Design as solid a pattern as possible, and be common to Pin 1 (GND_OUT). Unused, connect to GND via a 0.1F capacitor. Unused, connect to GND via a 0.1F capacitor. Unused, connect to GND via a 0.1F capacitor. Unused, connect to GND. Unused, connect to GND via a 0.1F capacitor. Unused, connect to GND via a 0.1F capacitor. Unused, connect to GND via a 0.1F capacitor. Pin Pin name No. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 IREF_HV AFC_FIL CERA HPROT VPROT Notes on operation and processing when unused Connect to GND via a 10k resistor with an error of 1% or less with short pattern. Locate external parts as near as possible. Locate external parts as near as possible. Unused, connect to GND. Input with the condition of Fig. 14 on page 59. HCOMP_IN Unused, connect to VREG5. VCOMP_IN Unused, connect to VREG5. L2_FIL HP_IN H_DRV GND_H VS_IN HC_PARA GND_V MP_PARA DF_PARA EW_DRV V_OSC V_AGC VSAW0 VSAW1 V_DRV- V_DRV+ VTIM Vcc9 ABL_IN ABL_FIL IK_IN SABL_IN PRE_RGB Vcc_OUT B_OUT G_OUT R_OUT Connect a by-pass capacitor nearby with thick pattern. Connect a buffer as nearby as possible. Connect a buffer as nearby as possible. Connect a buffer as nearby as possible. Unused, connect to GND via a 0.1F capacitor. Unused, connect to GND. Connect a by-pass capacitor nearby with thick pattern. Unused, connect to VCC5. Use a capacitor, such as polypropylene, with a small tan. Locate external parts as close as possible. Design as solid a pattern as possible. Locates the register for pull-up as close as possible. Design as solid a pattern as possible. Input DC coupled. Locate external parts as close as possible. DPDT_OFF Unused, connect to GND. YF_OFF VM_OUT CLP_C BPH IREF_YC Vcc5 Y_IN CB_IN CR_IN F0 F1 SDA SCL SCP HS_IN VREG5 VBIAS Input DC coupled. Connect a by-pass capacitor nearby with thick pattern. Locate a NPN-Tr for feed-back and by-pass capacitors as close as possible. As horizontal deflection frequency is 33.75kHz, connect to GND. As horizontal deflection frequency is 33.75kHz, connect to Pin 29 (VREG5). Connect to GND via a 4.7k resistor with an error of 1% or less with a short pattern. Connect a by-pass capacitor nearby with thick pattern to flow approximately 80mA current. Unused, connect to GND. Connect a buffer as close as possible. VM_MOD Unused, connect to VCC5. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Table 4. Notes on The Operation of Each Pin - 72 - General-purpose V sawtooth wave output General-purpose V sawtooth wave output General-purpose V parabora wave output General-purpose V parabora wave output General-purpose V parabora wave output VSYNC input Application Circuit HD signal output H-pulse input V protect signal input Hold-down input V parabora wave output 0.1 0.1 0.01 2 100 100 100 100 100 100 100 100 34 CERA 15k 0.47 10k1 0.68 VBIAS 30 VREG5 29 HS_IN 28 SCP 27 100 SCL 26 100 SDA 25 F1 24 F0 23 CR_IN 22 CB_IN 21 YF_OFF VM_OUT VM_MOD CLP_C Y_IN 20 BPH Vcc5 IREF_YC 0.1 0.1 0.1 Y/Cb/Cr input I2C bus I/O 0.1 100 Sand-castle pulse output 9V 100 33 HPROT AFC_FIL 32 IREF_HV 31 470 10 2.7k 3.3k 10 2.7MHz ceramic oscillator 51 VS_IN HP_IN L2_FIL 50 49 48 47 46 45 44 43 42 41 40 39 0.1 38 V high-voltage fluctuation compensation signal input 10k V high-voltage fluctuation 10k compensation signal input 37 36 35 VPROT 9V V_AGC V_OSC VSAW1 VSAW0 GND_V EW_DRV DF_PARA MP_PARA HC_PARA 52 100 100 54 VTIM 55 Vcc9 4.7 57 ABL_FIL 58 IK_IN 59 SABL_IN 60 PRE_RGB 61 Vcc_OUT 62 B_OUT 100 63 G_OUT GND_SIG B2_IN G2_IN R2_IN YSYM1 B1_IN G1_IN R1_IN PABL_FIL GND_OUT YSYM2 DPDT_OFF 64 R_OUT 100 56 ABL_IN V_DRV- 53 V_DRV+ GND_H H_DRV 100 VCOMP_IN V timing pulse output 0.1 9V 100 HCOMP_IN V sawtooth wave output 0.0047 ABL input HSYNC input 10k 0.1 0.1 0.1 0.1 0.1 100 0.1 100 0.1 100 100 100 100 0.47 0.47 4.7 VM output YS/YM input 2 Analog RGB input 2 YS/YM input 1 Analog RGB input 1 VM/COLOR Mute input DPIC/DC-TRAN Mute input VM level modulation input - 73 - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 1 4.7k 0.1 3.3M 5V 0.47 IK input LPF High-voltage distortion conpensation output 100 0.1 Horizontal deflection frequency settings 3 9V 100 100 9V 9V 9V B output G output R output 1 A metal film resister is recommended 2 A PP capacitor is recommended 3 See Table 1 on page 44 100 CXA2150AQ Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. CXA2150AQ Curve Data (I2C bus data conforms to the "I2C bus Register Initial Setting" of the Electrical Characteristics Measurement Conditions (P. 20).) 1) V_DRV+ 4.4 4.2 4.0 3.8 V [V] 3.6 3.4 3.2 3.0 2.8 0 5 10 Time [ms] 15 20 V [V] V_SIZE = 0 V_SIZE = 1F V_SIZE = 3F V_SIZE 4.4 4.2 4.0 3.8 3.6 3.4 3.2 3.0 2.8 0 5 V_POSITION V_POSITION = 0 V_POSITION = 1F V_POSITION = 3F 10 Time [ms] 15 20 S_CORRECTION 4.2 4.0 3.8 3.6 V [V] V [V] 3.4 3.2 3.0 2.8 0 5 10 Time [ms] 15 20 S_CORRECTION = 0 S_CORRECTION = 7 S_CORRECTION = F 4.2 4.0 3.8 3.6 3.4 3.2 3.0 2.8 0 5 V_LIN V_LIN = 0 V_LIN = 7 V_LIN = F 10 Time [ms] 15 20 V_ASPECT 4.4 4.2 4.0 3.8 V [V] V [V] 3.6 3.4 3.2 3.0 2.8 2.6 0 5 10 Time [ms] 15 20 V_ASPECT = 0 V_ASPECT = 1F V_ASPECT = 3F 4.4 4.2 4.0 3.8 3.6 3.4 3.2 3.0 2.8 2.6 0 5 V_SCROLL V_SCROLL = 0 V_SCROLL = 1F V_SCROLL = 3F 10 Time [ms] 15 20 - 74 - CXA2150AQ UP_VLIN 4.2 4.0 3.8 3.6 3.4 3.2 3.0 2.8 0 5 10 Time [ms] 15 20 UP_VLIN = 0 UP_VLIN = 7 UP_VLIN = F 4.2 4.0 3.8 3.6 3.4 3.2 3.0 2.8 0 5 LO_VLIN LO_VLIN = 0 LO_VLIN = 7 LO_VLIN = F V [V] V [V] 10 Time [ms] 15 20 JMP_SW 4.2 4.0 3.8 3.6 3.4 3.2 3.0 2.8 0 5 10 Time [ms] 15 20 JMP_SW = 0 JMP_SW = 1 4.5 4.4 4.3 4.2 4.1 V [V] 4.0 3.9 3.8 3.7 3.6 3.5 0 VDRV_SW (0 to 5ms magnification) VDRV_SW = 0 VDRV_SW = 1 V [V] 1 2 3 4 5 Time [ms] ASP_SW 4.4 4.2 4.0 3.8 V [V] 3.6 3.4 3.2 3.0 2.8 0 5 10 Time [ms] 15 20 ASP_SW = 0 ASP_SW = 1 - 75 - CXA2150AQ 2) V_SAW0, 1 VSAW0_AMP 4.7 4.7 VSAW1_AMP 4.5 4.5 4.3 V [V] V [V] VSAW0 _AMP = 0 VSAW0_AMP = F VSAW0_AMP = 1F 0 5 10 Time [ms] 15 20 4.3 4.1 4.1 3.9 3.7 3.9 3.7 VSAW1_AMP = 0 VSAW1_AMP = F VSAW1_AMP = 1F 0 5 10 Time [ms] 15 20 3.5 3.5 VSAW0_DC 5.5 5.5 VSAW1_DC 5.0 5.0 4.5 V [V] V [V] VSAW0_DCL = 0, VSAW0_DCH = 0 VSAW0_DCL = F, VSAW0_DCH = 1 VSAW0_DCL = F, VSAW0_DCH = 3 4.5 4.0 4.0 VSAW1_DC = 0 VSAW1_DC = F VSAW1_DC = 7 3.5. 3.0 3.5. 3.0 2.5 0 5 10 Time [ms] 15 20 2.5 0 5 10 Time [ms] 15 20 - 76 - CXA2150AQ 3) EW_DRV H_SIZE 4.6 4.1 4.0 4.2 3.9 3.8 3.8 V [V] V [V] 3.7 3.6 3.5 3.0 H_SIZE = 0 H_SIZE = 1F H_SIZE = 3F 0 5 10 Time [ms] 15 20 3.4 3.3 3.2 0 5 PIN_PHASE 3.4 PIN_PHASE = 0 PIN_PHASE = 1F PIN_PHASE = 3F 10 Time [ms] 15 20 2.6 UP_CPIN 4.2 4.1 4.0 4.0 3.9 3.8 V [V] V [V] 3.8 3.7 3.6 3.5 UP_CPIN = 0 UP_CPIN = 1F UP_CPIN = 3F 0 5 10 Time [ms] 15 20 3.4 3.3 3.2 0 5 LO_CPIN 3.6 3.4 3.2 LO_CPIN = 0 LO_CPIN = 1F LO_CPIN = 3F 10 Time [ms] 15 20 3.0 UP_UCG 4.2 4.0 3.8 3.6 V [V] 3.4 3.2 3.0 2.8 2.6 0 5 10 Time [ms] 15 20 UP_UCG = 0 UP_UCG = 3 (UC_POL = 0) UP_UCG = 3 (UC_POL = 1) 3.2 3.0 2.8 0 5 V [V] 3.6 3.4 4.2 4.0 3.8 LO_UCG LO_UCG = 0 LO_UCG = 3 (UC_POL = 0) LO_UCG = 3 (UC_POL = 1) 10 Time [ms] 15 20 - 77 - CXA2150AQ UP_UCP 4.2 4.2 LO_UCP 4.0 4.0 3.8 V [V] V [V] UP_UCP = 0 UP_UCP = 3 3.8 3.6 3.6 3.4 3.4 LO_UCP = 0 LO_UCP = 3 3.2 3.2 3.0 0 5 10 Time [ms] 15 20 3.0 0 5 10 Time [ms] 15 20 PIN_AMP 4.2 4.2 EW_DC 4.0 3.8 3.8 3.4 V [V] 3.6 V [V] 3.0 3.4 PIN_AMP = 0 PIN_AMP = 1F PIN_AMP = 3F 0 5 10 Time [ms] 15 20 2.6 EW_DC = 0 EW_DC = 1 2.2 0 5 10 Time [ms] 15 20 3.2 3.0 - 78 - CXA2150AQ 4) MP_PARA, HC_PARA, DF_PARA MP_PARA_DC 4.5 3.8 MP_PARA_AMP 4.0 3.6 3.4 3.5 V [V] V [V] 3.0 MP_PARA_DC = 0 MP_PARA_DC = 7 MP_PARA_DC = F 3.0 MP_PARA_AMP = 0 MP_PARA_AMP = 7 MP_PARA_AMP = F 0 5 10 Time [ms] 15 20 2.5 2.0 0 5 10 Time [ms] 15 20 3.2 2.8 2.6 HC_PARA_DC 4.7 4.0 HC_PARA_AMP 4.2 3.8 3.6 3.7 V [V] V [V] 3.2 HC_PARA_DC = 0 HC_PARA_DC = 1F HC_PARA_DC = 3F 3.2 HC_PARA_AMP = 0 HC_PARA_AMP = 1F HC_PARA_AMP = 3F 0 5 10 Time [ms] 15 20 2.7 2.2 0 5 10 Time [ms] 15 20 3.4 3.0 2.8 HC_PARA_PHASE 4.0 HC_PARA_PHASE = 0 HC_PARA_PHASE = 1F HC_PARA_PHASE = 3F DF_PARA 4.2 3.8 4.0 3.8 3.6 V [V] V [V] 3.4 3.4 3.2 3.0 0 5 10 Time [ms] 15 20 3.6 3.2 3.0 0 5 10 Time [ms] 15 20 - 79 - CXA2150AQ 5) HP_IN, SCP H_POSITION (See Fig. 13 on page 58) 6 Phpos - Input SYNC reference HP phase [%] Pclp - Input SYNC reference CLP phase [%] 5 4 3 2 1 0 -1 0 31 DATA Prblk - Input SYNC reference RIGHT_BLK phase [%] 62 10 9 8 7 6 5 4 3 2 1 0 0 0.5 1.0 1.5 DATA 2.0 2.5 3.0 Front adge Back adge CLP_PHASE (See Fig. 13 on page 58) 0 -2 -4 -6 -8 -10 -12 -14 0 31 DATA 62 Plblk - Input SYNC reference LEFT_BLK phase [%] RIGHT_BLK (See Fig. 13 on page 58) LEFT_BLK (See Fig. 13 on page 58) 18 16 14 12 10 8 6 0 31 DATA 62 AFC_ANGLE 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 0 31 DATA 62 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 0 AFC_BOW Phase [%] Phase [%] 31 DATA 62 - 80 - CXA2150AQ 6) High Voltage Compensation V_COMP (V_COMPIN = 0V) 4.4 4.2 4.0 3.8 V [V] 3.6 3.4 3.2 90 3.0 2.8 0 5 10 Time [ms] 15 20 88 0 1 2 3 4 5 6 VCOMP_IN [V] V_COMP = 0 V_COMP = 7 V_COMP = F V_DRV amplitude [%] 96 100 98 V_COMP 94 92 PIN_COMP (H_COMPIN = 0V) 4.0 3.9 EW_DRV amplitude [%] 3.8 3.7 V [V] 3.6 3.5 3.4 3.3 3.2 0 5 10 Time [ms] 15 20 PIN_COMP = 0 PIN_COMP = 3 PIN_COMP = 7 100 98 PINCOMP 96 94 92 90 88 0 1 2 3 4 5 6 HCOMP_IN [V] H_COMP (H_COMPIN = 0V) 4.0 3.9 -0.10 EW_DC variable amount [V] 3.8 3.7 3.6 V [V] 3.5 3.4 3.3 3.2 3.1 3.0 0 5 10 Time [ms] 15 20 H_COMP = 0 H_COMP = 7 H_COMP = F -0.15 -0.20 -0.25 -0.30 -0.35 -0.40 0 1 2 0 H_COMP 3 4 5 6 HCOMP_IN [V] - 81 - CXA2150AQ AFC_COMP (HCOMP_IN = 0V) 2.0 1.8 Phase compensation amount [%] 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 3 DATA 6 Phase compensation amount [%] 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 1 AFC_COMP AFC_COMP = 3 AFC_COMP = 7 2 3 4 5 HCOMP_IN [V] - 82 - CXA2150AQ 7) Signal System SUB_CONT 1.5 1.0 R, G and B output level [V] R, G and B output level [V] 10 5 0 -5 -10 -15 -20 -25 0 7 DATA 14 0 31 DATA 62 COLOR 0.5 0 -0.5 -1.0 -1.5 Y_OFFSET 50 40 30 Rch output voltage [mV] 20 10 0 -10 -20 -30 -40 0 7 DATA 14 Bch output voltage [mV] 80 60 40 20 0 -20 -40 -60 -80 0 CB_OFFSET 31 DATA 62 CR_OFFSET 80 60 Rch output voltage [mV] 40 20 0 -20 -40 -60 -80 0 31 DATA 62 R, G and B output level [dB] 0 -2 -4 -6 -8 -10 -12 -14 0 PICTURE 31 DATA 62 - 83 - CXA2150AQ BRIGHT, SUB_BRIGHT 20 15 R, G and B output level [dB] 10 5 0 -5 -10 -15 0 31 DATA 62 2 1 0 -1 -2 -3 -4 -5 0 DRIVE Pedestal level [IRE] 31 DATA 62 GAMMA 3.0 6 4 R, G and B output level [Vp-p] 2.5 2 2.0 IK return level [dB] 0 -2 -4 -6 -8 -10 -12 0 20 40 60 80 100 0 CUTOFF 1.5 1.0 GAMMA = 0 GAMMA = 1 GAMMA = 2 GAMMA = 3 0.5 0 Input level [IRE] 31 DATA 62 AKB_LOOP lock range 4.5 4.0 Reference pulse voltage [V] 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 1 2 3 4 CRTDC [V] (See page 17) ROUT reference pulse level [V] 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 CUT_OFF (AKBOFF = 1, BLK_OFF = 1) 0 31 DATA 62 - 84 - CXA2150AQ DPIC_LEV 70 60 R, G and B output level [Vp-p] 50 40 30 20 10 0 0 20 40 60 Input level [IRE] RGB output level [dB] 0 ABL_MODE Characteristics (PICTURE) -5 -10 -15 -20 ABL_MODE = 0 ABL_MODE = 1 ABL_MODE = 2 ABL_MODE = 3 0 1 2 3 4 5 DPIC_LEV = 0 DPIC_LEV = 1 DPIC_LEV = 2 DPIC_LEV = 3 -25 -30 ABL_FIL voltage [V] ABL_MODE Characteristics (BRIGHT) 0 -5 -0 Pedestal [IRE] -15 -20 -25 -30 -35 -40 0 1 2 3 4 5 ABL_FIL voltage [V] ABL_MODE = 0 ABL_MODE = 1 ABL_MODE = 2 ABL_MODE = 3 110 100 RGB output level [IRE] 90 80 70 60 50 40 2.0 S_ABL S_ABL = 0 S_ABL = 1 S_ABL = 2 2.2 2.4 2.6 2.8 3.0 SABL_IN voltage [V] ABL_TH (Threshold in quick charge and normal charge) 5 65 ABL_TH (Threshold in quick discharge) 4 55 3 ABL_FIL voltage [mV] ABL_TH = 0 ABL_TH = 7 ABL_TH = F 0 1 2 ABL_IN voltage [V] 3 4 ABL_FIL voltage [V] 45 2 35 ABL_TH = 0 ABL_TH = 7 ABL_TH = F 1 0 25 0 0.5 1.0 ABL_IN voltage [V] 1.5 2.0 - 85 - CXA2150AQ COL_AXIS = 3 (NTSC JAPAN) R-Y 1.0 COL_AXIS = 2 (NTSC US) R-Y 1.0 R-Y 0.5 R-Y 0.5 0 -1.0 -0.5 0 0.5 1.0 B-Y 0 -1.0 -0.5 0 0.5 1.0 B-Y G-Y -0.5 G-Y -0.5 -1.0 -1.0 COL_AXIS = 1 (PAL/SECAM) R-Y 1.0 COL_AXIS = 0 (NTSC Projecter) R-Y 1.0 R-Y R-Y 0.5 0.5 0 -1.0 -0.5 0 0.5 1.0 B-Y 0 -1.0 -0.5 0 0.5 1.0 B-Y G-Y -0.5 G-Y -0.5 -1.0 -1.0 Detection Axis Adjustment - 86 - CXA2150AQ 8) Frequency Response YIN RGB_OUT SHARPNESS (SYSTEM = 2 (HD), SHP_F0 = 0) 8 6 4 2 0 -2 -4 -6 -8 -10 -12 0 5 10 15 20 Gain [dB] SHARPNESS = 0 SHARPNESS = 1F SHARPNESS = 3F 25 30 35 40 45 Frequency [MHz] YIN RGB_OUT SHARPNESS OFF (YF_OFF = 1.5V, SHP_F0 = 0) 6 3 Gain [dB] 0 -3 -6 -9 0.1 DTV HD FF N 1 Frequency [MHz] 10 100 RGB1, 2_IN RGB_OUT 2 1 Gain [dB] 0 -1 -2 -3 0.1 RGB1 RGB2 1 Frequency [MHz] 10 100 CB_IN B_OUT (SHP_F0 = 0) 3 0 Gain [dB] -3 -6 -9 0.1 NORMAL FF HD DTV 1 Frequency [MHz] 10 100 - 87 - CXA2150AQ 9) VM_OUT Characteristics (SYSTEM = 2, SHP_F0 = 0) VM_F0 = 0 0 -6 Gain [dB] -12 -18 -24 -30 -36 0 10 20 Frequency [MHz] 30 40 VM_F0 = 1 0 -6 -12 Gain [dB] -18 -24 -30 -36 -42 0 10 20 Frequency [MHz] 30 40 VM_F0 = 2 0 -6 -12 Gain [dB] -18 -24 -30 -36 -42 0 10 20 Frequency [MHz] 30 40 VM_MOD 3.0 2.5 VM_OUT output level [Vp-p] VM_LEV = 1 VM_LEV = 2 VM_LEV = 3 2.0 1.5 1.0 0.5 0 1 2 3 VM_MOD voltage [V] 4 5 - 88 - CXA2150AQ SYSTEM = 0 (NORMAL) 160 140 120 100 tVM-R [ns] 80 60 40 20 0 -20 0 1 VM_DLY 2 3 VM_F0 = 0, SHP_F0 = 0 VM_F0 = 2, SHP_F0 = 0 VM_F0 = 0, SHP_F0 = 1 VM_F0 = 2, SHP_F0 = 1 SYSTEM = 1 (FF) 90 80 70 60 tVM-R [ns] 50 40 30 20 10 0 0 1 VM_DLY 2 3 VM_F0 = 0, SHP_F0 = 0 VM_F0 = 2, SHP_F0 = 0 VM_F0 = 0, SHP_F0 = 1 VM_F0 = 2, SHP_F0 = 1 SYSTEM = 2 (HD) 90 80 70 60 tVM-R [ns] tVM-R [ns] 50 40 30 20 10 0 0 1 VM_DLY 2 3 VM_F0 = 0, SHP_F0 = 0 VM_F0 = 2, SHP_F0 = 0 VM_F0 = 0, SHP_F0 = 1 VM_F0 = 2, SHP_F0 = 1 SYSTEM = 3 (DTV) 90 80 70 60 50 40 30 20 10 0 0 1 VM_DLY 2 3 VM_F0 = 0, SHP_F0 = 0 VM_F0 = 2, SHP_F0 = 0 VM_F0 = 0, SHP_F0 = 1 VM_F0 = 2, SHP_F0 = 1 VM_OUT tVM-R R_OUT Y_IN: Phase Difference between VM_OUT and R_OUT when T-pulse Inputs - 89 - CXA2150AQ Package Outline Unit: mm 64PIN QFP(PLASTIC) 23.9 0.4 + 0.4 20.0 - 0.1 51 33 + 0.1 0.15 - 0.05 0.15 52 32 17.9 0.4 + 0.4 14.0 - 0.1 64 20 + 0.2 0.1 - 0.05 1 1.0 + 0.15 0.4 - 0.1 + 0.35 2.75 - 0.15 0.2 M 0 to10 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-64P-L01 QFP064-P-1420 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 1.5g NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). - 90 - 0.8 0.2 19 16.3 Sony Corporation |
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